Ronak Kanabar | 1ae366f | 2023-06-07 01:21:56 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | MSR Definitions for Intel(R) Xeon(R) Processor D product Family. |
| 3 | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not |
| 7 | provided for that MSR. |
| 8 | |
| 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> |
| 10 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 11 | |
| 12 | @par Specification Reference: |
| 13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR) |
| 15 | |
| 16 | **/ |
| 17 | |
| 18 | #ifndef __XEON_D_MSR_H__ |
| 19 | #define __XEON_D_MSR_H__ |
| 20 | |
| 21 | #include <Register/Intel/ArchitecturalMsr.h> |
| 22 | |
| 23 | /** |
| 24 | Is Intel(R) Xeon(R) Processor D product Family? |
| 25 | |
| 26 | @param DisplayFamily Display Family ID |
| 27 | @param DisplayModel Display Model ID |
| 28 | |
| 29 | @retval TRUE Yes, it is. |
| 30 | @retval FALSE No, it isn't. |
| 31 | **/ |
| 32 | #define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \ |
| 33 | (DisplayFamily == 0x06 && \ |
| 34 | ( \ |
| 35 | DisplayModel == 0x4F || \ |
| 36 | DisplayModel == 0x56 \ |
| 37 | ) \ |
| 38 | ) |
| 39 | |
| 40 | /** |
| 41 | Package. Protected Processor Inventory Number Enable Control (R/W). |
| 42 | |
| 43 | @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E) |
| 44 | @param EAX Lower 32-bits of MSR value. |
| 45 | Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. |
| 46 | @param EDX Upper 32-bits of MSR value. |
| 47 | Described by the type MSR_XEON_D_PPIN_CTL_REGISTER. |
| 48 | |
| 49 | <b>Example usage</b> |
| 50 | @code |
| 51 | MSR_XEON_D_PPIN_CTL_REGISTER Msr; |
| 52 | |
| 53 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL); |
| 54 | AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64); |
| 55 | @endcode |
| 56 | @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM. |
| 57 | **/ |
| 58 | #define MSR_XEON_D_PPIN_CTL 0x0000004E |
| 59 | |
| 60 | /** |
| 61 | MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL |
| 62 | **/ |
| 63 | typedef union { |
| 64 | /// |
| 65 | /// Individual bit fields |
| 66 | /// |
| 67 | struct { |
| 68 | /// |
| 69 | /// [Bit 0] LockOut (R/WO) See Table 2-25. |
| 70 | /// |
| 71 | UINT32 LockOut : 1; |
| 72 | /// |
| 73 | /// [Bit 1] Enable_PPIN (R/W) See Table 2-25. |
| 74 | /// |
| 75 | UINT32 Enable_PPIN : 1; |
| 76 | UINT32 Reserved1 : 30; |
| 77 | UINT32 Reserved2 : 32; |
| 78 | } Bits; |
| 79 | /// |
| 80 | /// All bit fields as a 32-bit value |
| 81 | /// |
| 82 | UINT32 Uint32; |
| 83 | /// |
| 84 | /// All bit fields as a 64-bit value |
| 85 | /// |
| 86 | UINT64 Uint64; |
| 87 | } MSR_XEON_D_PPIN_CTL_REGISTER; |
| 88 | |
| 89 | /** |
| 90 | Package. Protected Processor Inventory Number (R/O). Protected Processor |
| 91 | Inventory Number (R/O) See Table 2-25. |
| 92 | |
| 93 | @param ECX MSR_XEON_D_PPIN (0x0000004F) |
| 94 | @param EAX Lower 32-bits of MSR value. |
| 95 | @param EDX Upper 32-bits of MSR value. |
| 96 | |
| 97 | <b>Example usage</b> |
| 98 | @code |
| 99 | UINT64 Msr; |
| 100 | |
| 101 | Msr = AsmReadMsr64 (MSR_XEON_D_PPIN); |
| 102 | @endcode |
| 103 | @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM. |
| 104 | **/ |
| 105 | #define MSR_XEON_D_PPIN 0x0000004F |
| 106 | |
| 107 | /** |
| 108 | Package. See http://biosbits.org. |
| 109 | |
| 110 | @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE) |
| 111 | @param EAX Lower 32-bits of MSR value. |
| 112 | Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. |
| 113 | @param EDX Upper 32-bits of MSR value. |
| 114 | Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER. |
| 115 | |
| 116 | <b>Example usage</b> |
| 117 | @code |
| 118 | MSR_XEON_D_PLATFORM_INFO_REGISTER Msr; |
| 119 | |
| 120 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO); |
| 121 | AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64); |
| 122 | @endcode |
| 123 | @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM. |
| 124 | **/ |
| 125 | #define MSR_XEON_D_PLATFORM_INFO 0x000000CE |
| 126 | |
| 127 | /** |
| 128 | MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO |
| 129 | **/ |
| 130 | typedef union { |
| 131 | /// |
| 132 | /// Individual bit fields |
| 133 | /// |
| 134 | struct { |
| 135 | UINT32 Reserved1 : 8; |
| 136 | /// |
| 137 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25. |
| 138 | /// |
| 139 | UINT32 MaximumNonTurboRatio : 8; |
| 140 | UINT32 Reserved2 : 7; |
| 141 | /// |
| 142 | /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25. |
| 143 | /// |
| 144 | UINT32 PPIN_CAP : 1; |
| 145 | UINT32 Reserved3 : 4; |
| 146 | /// |
| 147 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See |
| 148 | /// Table 2-25. |
| 149 | /// |
| 150 | UINT32 RatioLimit : 1; |
| 151 | /// |
| 152 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See |
| 153 | /// Table 2-25. |
| 154 | /// |
| 155 | UINT32 TDPLimit : 1; |
| 156 | /// |
| 157 | /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25. |
| 158 | /// |
| 159 | UINT32 TJOFFSET : 1; |
| 160 | UINT32 Reserved4 : 1; |
| 161 | UINT32 Reserved5 : 8; |
| 162 | /// |
| 163 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25. |
| 164 | /// |
| 165 | UINT32 MaximumEfficiencyRatio : 8; |
| 166 | UINT32 Reserved6 : 16; |
| 167 | } Bits; |
| 168 | /// |
| 169 | /// All bit fields as a 64-bit value |
| 170 | /// |
| 171 | UINT64 Uint64; |
| 172 | } MSR_XEON_D_PLATFORM_INFO_REGISTER; |
| 173 | |
| 174 | /** |
| 175 | Core. C-State Configuration Control (R/W) Note: C-state values are processor |
| 176 | specific C-state code names, unrelated to MWAIT extension C-state parameters |
| 177 | or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__. |
| 178 | |
| 179 | @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2) |
| 180 | @param EAX Lower 32-bits of MSR value. |
| 181 | Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. |
| 182 | @param EDX Upper 32-bits of MSR value. |
| 183 | Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER. |
| 184 | |
| 185 | <b>Example usage</b> |
| 186 | @code |
| 187 | MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr; |
| 188 | |
| 189 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL); |
| 190 | AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64); |
| 191 | @endcode |
| 192 | @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. |
| 193 | **/ |
| 194 | #define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2 |
| 195 | |
| 196 | /** |
| 197 | MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL |
| 198 | **/ |
| 199 | typedef union { |
| 200 | /// |
| 201 | /// Individual bit fields |
| 202 | /// |
| 203 | struct { |
| 204 | /// |
| 205 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest |
| 206 | /// processor-specific C-state code name (consuming the least power) for |
| 207 | /// the package. The default is set as factory-configured package C-state |
| 208 | /// limit. The following C-state code name encodings are supported: 000b: |
| 209 | /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) |
| 210 | /// 011b: C6 (retention) 111b: No Package C state limits. All C states |
| 211 | /// supported by the processor are available. |
| 212 | /// |
| 213 | UINT32 Limit : 3; |
| 214 | UINT32 Reserved1 : 7; |
| 215 | /// |
| 216 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W). |
| 217 | /// |
| 218 | UINT32 IO_MWAIT : 1; |
| 219 | UINT32 Reserved2 : 4; |
| 220 | /// |
| 221 | /// [Bit 15] CFG Lock (R/WO). |
| 222 | /// |
| 223 | UINT32 CFGLock : 1; |
| 224 | /// |
| 225 | /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor |
| 226 | /// will convert HALT or MWAT(C1) to MWAIT(C6). |
| 227 | /// |
| 228 | UINT32 CStateConversion : 1; |
| 229 | UINT32 Reserved3 : 8; |
| 230 | /// |
| 231 | /// [Bit 25] C3 State Auto Demotion Enable (R/W). |
| 232 | /// |
| 233 | UINT32 C3AutoDemotion : 1; |
| 234 | /// |
| 235 | /// [Bit 26] C1 State Auto Demotion Enable (R/W). |
| 236 | /// |
| 237 | UINT32 C1AutoDemotion : 1; |
| 238 | /// |
| 239 | /// [Bit 27] Enable C3 Undemotion (R/W). |
| 240 | /// |
| 241 | UINT32 C3Undemotion : 1; |
| 242 | /// |
| 243 | /// [Bit 28] Enable C1 Undemotion (R/W). |
| 244 | /// |
| 245 | UINT32 C1Undemotion : 1; |
| 246 | /// |
| 247 | /// [Bit 29] Package C State Demotion Enable (R/W). |
| 248 | /// |
| 249 | UINT32 CStateDemotion : 1; |
| 250 | /// |
| 251 | /// [Bit 30] Package C State UnDemotion Enable (R/W). |
| 252 | /// |
| 253 | UINT32 CStateUndemotion : 1; |
| 254 | UINT32 Reserved4 : 1; |
| 255 | UINT32 Reserved5 : 32; |
| 256 | } Bits; |
| 257 | /// |
| 258 | /// All bit fields as a 32-bit value |
| 259 | /// |
| 260 | UINT32 Uint32; |
| 261 | /// |
| 262 | /// All bit fields as a 64-bit value |
| 263 | /// |
| 264 | UINT64 Uint64; |
| 265 | } MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER; |
| 266 | |
| 267 | /** |
| 268 | Thread. Global Machine Check Capability (R/O). |
| 269 | |
| 270 | @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179) |
| 271 | @param EAX Lower 32-bits of MSR value. |
| 272 | Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. |
| 273 | @param EDX Upper 32-bits of MSR value. |
| 274 | Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER. |
| 275 | |
| 276 | <b>Example usage</b> |
| 277 | @code |
| 278 | MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr; |
| 279 | |
| 280 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP); |
| 281 | @endcode |
| 282 | @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM. |
| 283 | **/ |
| 284 | #define MSR_XEON_D_IA32_MCG_CAP 0x00000179 |
| 285 | |
| 286 | /** |
| 287 | MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP |
| 288 | **/ |
| 289 | typedef union { |
| 290 | /// |
| 291 | /// Individual bit fields |
| 292 | /// |
| 293 | struct { |
| 294 | /// |
| 295 | /// [Bits 7:0] Count. |
| 296 | /// |
| 297 | UINT32 Count : 8; |
| 298 | /// |
| 299 | /// [Bit 8] MCG_CTL_P. |
| 300 | /// |
| 301 | UINT32 MCG_CTL_P : 1; |
| 302 | /// |
| 303 | /// [Bit 9] MCG_EXT_P. |
| 304 | /// |
| 305 | UINT32 MCG_EXT_P : 1; |
| 306 | /// |
| 307 | /// [Bit 10] MCP_CMCI_P. |
| 308 | /// |
| 309 | UINT32 MCP_CMCI_P : 1; |
| 310 | /// |
| 311 | /// [Bit 11] MCG_TES_P. |
| 312 | /// |
| 313 | UINT32 MCG_TES_P : 1; |
| 314 | UINT32 Reserved1 : 4; |
| 315 | /// |
| 316 | /// [Bits 23:16] MCG_EXT_CNT. |
| 317 | /// |
| 318 | UINT32 MCG_EXT_CNT : 8; |
| 319 | /// |
| 320 | /// [Bit 24] MCG_SER_P. |
| 321 | /// |
| 322 | UINT32 MCG_SER_P : 1; |
| 323 | /// |
| 324 | /// [Bit 25] MCG_EM_P. |
| 325 | /// |
| 326 | UINT32 MCG_EM_P : 1; |
| 327 | /// |
| 328 | /// [Bit 26] MCG_ELOG_P. |
| 329 | /// |
| 330 | UINT32 MCG_ELOG_P : 1; |
| 331 | UINT32 Reserved2 : 5; |
| 332 | UINT32 Reserved3 : 32; |
| 333 | } Bits; |
| 334 | /// |
| 335 | /// All bit fields as a 32-bit value |
| 336 | /// |
| 337 | UINT32 Uint32; |
| 338 | /// |
| 339 | /// All bit fields as a 64-bit value |
| 340 | /// |
| 341 | UINT64 Uint64; |
| 342 | } MSR_XEON_D_IA32_MCG_CAP_REGISTER; |
| 343 | |
| 344 | /** |
| 345 | THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability |
| 346 | Enhancement. Accessible only while in SMM. |
| 347 | |
| 348 | @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D) |
| 349 | @param EAX Lower 32-bits of MSR value. |
| 350 | Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. |
| 351 | @param EDX Upper 32-bits of MSR value. |
| 352 | Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER. |
| 353 | |
| 354 | <b>Example usage</b> |
| 355 | @code |
| 356 | MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr; |
| 357 | |
| 358 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP); |
| 359 | AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64); |
| 360 | @endcode |
| 361 | @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM. |
| 362 | **/ |
| 363 | #define MSR_XEON_D_SMM_MCA_CAP 0x0000017D |
| 364 | |
| 365 | /** |
| 366 | MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP |
| 367 | **/ |
| 368 | typedef union { |
| 369 | /// |
| 370 | /// Individual bit fields |
| 371 | /// |
| 372 | struct { |
| 373 | UINT32 Reserved1 : 32; |
| 374 | UINT32 Reserved2 : 26; |
| 375 | /// |
| 376 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the |
| 377 | /// SMM code access restriction is supported and a host-space interface |
| 378 | /// available to SMM handler. |
| 379 | /// |
| 380 | UINT32 SMM_Code_Access_Chk : 1; |
| 381 | /// |
| 382 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the |
| 383 | /// SMM long flow indicator is supported and a host-space interface |
| 384 | /// available to SMM handler. |
| 385 | /// |
| 386 | UINT32 Long_Flow_Indication : 1; |
| 387 | UINT32 Reserved3 : 4; |
| 388 | } Bits; |
| 389 | /// |
| 390 | /// All bit fields as a 64-bit value |
| 391 | /// |
| 392 | UINT64 Uint64; |
| 393 | } MSR_XEON_D_SMM_MCA_CAP_REGISTER; |
| 394 | |
| 395 | /** |
| 396 | Package. |
| 397 | |
| 398 | @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2) |
| 399 | @param EAX Lower 32-bits of MSR value. |
| 400 | Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER. |
| 401 | @param EDX Upper 32-bits of MSR value. |
| 402 | Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER. |
| 403 | |
| 404 | <b>Example usage</b> |
| 405 | @code |
| 406 | MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr; |
| 407 | |
| 408 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET); |
| 409 | AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64); |
| 410 | @endcode |
| 411 | @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM. |
| 412 | **/ |
| 413 | #define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2 |
| 414 | |
| 415 | /** |
| 416 | MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET |
| 417 | **/ |
| 418 | typedef union { |
| 419 | /// |
| 420 | /// Individual bit fields |
| 421 | /// |
| 422 | struct { |
| 423 | UINT32 Reserved1 : 16; |
| 424 | /// |
| 425 | /// [Bits 23:16] Temperature Target (RO) See Table 2-25. |
| 426 | /// |
| 427 | UINT32 TemperatureTarget : 8; |
| 428 | /// |
| 429 | /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25. |
| 430 | /// |
| 431 | UINT32 TCCActivationOffset : 4; |
| 432 | UINT32 Reserved2 : 4; |
| 433 | UINT32 Reserved3 : 32; |
| 434 | } Bits; |
| 435 | /// |
| 436 | /// All bit fields as a 32-bit value |
| 437 | /// |
| 438 | UINT32 Uint32; |
| 439 | /// |
| 440 | /// All bit fields as a 64-bit value |
| 441 | /// |
| 442 | UINT64 Uint64; |
| 443 | } MSR_XEON_D_TEMPERATURE_TARGET_REGISTER; |
| 444 | |
| 445 | /** |
| 446 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, |
| 447 | RW if MSR_PLATFORM_INFO.[28] = 1. |
| 448 | |
| 449 | @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD) |
| 450 | @param EAX Lower 32-bits of MSR value. |
| 451 | Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER. |
| 452 | @param EDX Upper 32-bits of MSR value. |
| 453 | Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER. |
| 454 | |
| 455 | <b>Example usage</b> |
| 456 | @code |
| 457 | MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr; |
| 458 | |
| 459 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT); |
| 460 | @endcode |
| 461 | @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. |
| 462 | **/ |
| 463 | #define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD |
| 464 | |
| 465 | /** |
| 466 | MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT |
| 467 | **/ |
| 468 | typedef union { |
| 469 | /// |
| 470 | /// Individual bit fields |
| 471 | /// |
| 472 | struct { |
| 473 | /// |
| 474 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C. |
| 475 | /// |
| 476 | UINT32 Maximum1C : 8; |
| 477 | /// |
| 478 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C. |
| 479 | /// |
| 480 | UINT32 Maximum2C : 8; |
| 481 | /// |
| 482 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C. |
| 483 | /// |
| 484 | UINT32 Maximum3C : 8; |
| 485 | /// |
| 486 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C. |
| 487 | /// |
| 488 | UINT32 Maximum4C : 8; |
| 489 | /// |
| 490 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C. |
| 491 | /// |
| 492 | UINT32 Maximum5C : 8; |
| 493 | /// |
| 494 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C. |
| 495 | /// |
| 496 | UINT32 Maximum6C : 8; |
| 497 | /// |
| 498 | /// [Bits 55:48] Package. Maximum Ratio Limit for 7C. |
| 499 | /// |
| 500 | UINT32 Maximum7C : 8; |
| 501 | /// |
| 502 | /// [Bits 63:56] Package. Maximum Ratio Limit for 8C. |
| 503 | /// |
| 504 | UINT32 Maximum8C : 8; |
| 505 | } Bits; |
| 506 | /// |
| 507 | /// All bit fields as a 64-bit value |
| 508 | /// |
| 509 | UINT64 Uint64; |
| 510 | } MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER; |
| 511 | |
| 512 | /** |
| 513 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, |
| 514 | RW if MSR_PLATFORM_INFO.[28] = 1. |
| 515 | |
| 516 | @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE) |
| 517 | @param EAX Lower 32-bits of MSR value. |
| 518 | Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER. |
| 519 | @param EDX Upper 32-bits of MSR value. |
| 520 | Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER. |
| 521 | |
| 522 | <b>Example usage</b> |
| 523 | @code |
| 524 | MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr; |
| 525 | |
| 526 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1); |
| 527 | @endcode |
| 528 | @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM. |
| 529 | **/ |
| 530 | #define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE |
| 531 | |
| 532 | /** |
| 533 | MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1 |
| 534 | **/ |
| 535 | typedef union { |
| 536 | /// |
| 537 | /// Individual bit fields |
| 538 | /// |
| 539 | struct { |
| 540 | /// |
| 541 | /// [Bits 7:0] Package. Maximum Ratio Limit for 9C. |
| 542 | /// |
| 543 | UINT32 Maximum9C : 8; |
| 544 | /// |
| 545 | /// [Bits 15:8] Package. Maximum Ratio Limit for 10C. |
| 546 | /// |
| 547 | UINT32 Maximum10C : 8; |
| 548 | /// |
| 549 | /// [Bits 23:16] Package. Maximum Ratio Limit for 11C. |
| 550 | /// |
| 551 | UINT32 Maximum11C : 8; |
| 552 | /// |
| 553 | /// [Bits 31:24] Package. Maximum Ratio Limit for 12C. |
| 554 | /// |
| 555 | UINT32 Maximum12C : 8; |
| 556 | /// |
| 557 | /// [Bits 39:32] Package. Maximum Ratio Limit for 13C. |
| 558 | /// |
| 559 | UINT32 Maximum13C : 8; |
| 560 | /// |
| 561 | /// [Bits 47:40] Package. Maximum Ratio Limit for 14C. |
| 562 | /// |
| 563 | UINT32 Maximum14C : 8; |
| 564 | /// |
| 565 | /// [Bits 55:48] Package. Maximum Ratio Limit for 15C. |
| 566 | /// |
| 567 | UINT32 Maximum15C : 8; |
| 568 | /// |
| 569 | /// [Bits 63:56] Package. Maximum Ratio Limit for 16C. |
| 570 | /// |
| 571 | UINT32 Maximum16C : 8; |
| 572 | } Bits; |
| 573 | /// |
| 574 | /// All bit fields as a 64-bit value |
| 575 | /// |
| 576 | UINT64 Uint64; |
| 577 | } MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER; |
| 578 | |
| 579 | /** |
| 580 | Package. Unit Multipliers used in RAPL Interfaces (R/O). |
| 581 | |
| 582 | @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606) |
| 583 | @param EAX Lower 32-bits of MSR value. |
| 584 | Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER. |
| 585 | @param EDX Upper 32-bits of MSR value. |
| 586 | Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER. |
| 587 | |
| 588 | <b>Example usage</b> |
| 589 | @code |
| 590 | MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr; |
| 591 | |
| 592 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT); |
| 593 | @endcode |
| 594 | @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM. |
| 595 | **/ |
| 596 | #define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606 |
| 597 | |
| 598 | /** |
| 599 | MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT |
| 600 | **/ |
| 601 | typedef union { |
| 602 | /// |
| 603 | /// Individual bit fields |
| 604 | /// |
| 605 | struct { |
| 606 | /// |
| 607 | /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.". |
| 608 | /// |
| 609 | UINT32 PowerUnits : 4; |
| 610 | UINT32 Reserved1 : 4; |
| 611 | /// |
| 612 | /// [Bits 12:8] Package. Energy Status Units Energy related information |
| 613 | /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an |
| 614 | /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61 |
| 615 | /// micro-joules). |
| 616 | /// |
| 617 | UINT32 EnergyStatusUnits : 5; |
| 618 | UINT32 Reserved2 : 3; |
| 619 | /// |
| 620 | /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL |
| 621 | /// Interfaces.". |
| 622 | /// |
| 623 | UINT32 TimeUnits : 4; |
| 624 | UINT32 Reserved3 : 12; |
| 625 | UINT32 Reserved4 : 32; |
| 626 | } Bits; |
| 627 | /// |
| 628 | /// All bit fields as a 32-bit value |
| 629 | /// |
| 630 | UINT32 Uint32; |
| 631 | /// |
| 632 | /// All bit fields as a 64-bit value |
| 633 | /// |
| 634 | UINT64 Uint64; |
| 635 | } MSR_XEON_D_RAPL_POWER_UNIT_REGISTER; |
| 636 | |
| 637 | /** |
| 638 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL |
| 639 | Domain.". |
| 640 | |
| 641 | @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618) |
| 642 | @param EAX Lower 32-bits of MSR value. |
| 643 | @param EDX Upper 32-bits of MSR value. |
| 644 | |
| 645 | <b>Example usage</b> |
| 646 | @code |
| 647 | UINT64 Msr; |
| 648 | |
| 649 | Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT); |
| 650 | AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr); |
| 651 | @endcode |
| 652 | @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM. |
| 653 | **/ |
| 654 | #define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618 |
| 655 | |
| 656 | /** |
| 657 | Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices. |
| 658 | |
| 659 | @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619) |
| 660 | @param EAX Lower 32-bits of MSR value. |
| 661 | Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER. |
| 662 | @param EDX Upper 32-bits of MSR value. |
| 663 | Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER. |
| 664 | |
| 665 | <b>Example usage</b> |
| 666 | @code |
| 667 | MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr; |
| 668 | |
| 669 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS); |
| 670 | @endcode |
| 671 | @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM. |
| 672 | **/ |
| 673 | #define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619 |
| 674 | |
| 675 | /** |
| 676 | MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS |
| 677 | **/ |
| 678 | typedef union { |
| 679 | /// |
| 680 | /// Individual bit fields |
| 681 | /// |
| 682 | struct { |
| 683 | /// |
| 684 | /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration |
| 685 | /// to enable DRAM RAPL mode 0 (Direct VR). |
| 686 | /// |
| 687 | UINT32 Energy : 32; |
| 688 | UINT32 Reserved : 32; |
| 689 | } Bits; |
| 690 | /// |
| 691 | /// All bit fields as a 32-bit value |
| 692 | /// |
| 693 | UINT32 Uint32; |
| 694 | /// |
| 695 | /// All bit fields as a 64-bit value |
| 696 | /// |
| 697 | UINT64 Uint64; |
| 698 | } MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER; |
| 699 | |
| 700 | /** |
| 701 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM |
| 702 | RAPL Domain.". |
| 703 | |
| 704 | @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B) |
| 705 | @param EAX Lower 32-bits of MSR value. |
| 706 | @param EDX Upper 32-bits of MSR value. |
| 707 | |
| 708 | <b>Example usage</b> |
| 709 | @code |
| 710 | UINT64 Msr; |
| 711 | |
| 712 | Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS); |
| 713 | @endcode |
| 714 | @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM. |
| 715 | **/ |
| 716 | #define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B |
| 717 | |
| 718 | /** |
| 719 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.". |
| 720 | |
| 721 | @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C) |
| 722 | @param EAX Lower 32-bits of MSR value. |
| 723 | @param EDX Upper 32-bits of MSR value. |
| 724 | |
| 725 | <b>Example usage</b> |
| 726 | @code |
| 727 | UINT64 Msr; |
| 728 | |
| 729 | Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO); |
| 730 | AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr); |
| 731 | @endcode |
| 732 | @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM. |
| 733 | **/ |
| 734 | #define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C |
| 735 | |
| 736 | /** |
| 737 | Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio |
| 738 | fields represent the widest possible range of uncore frequencies. Writing to |
| 739 | these fields allows software to control the minimum and the maximum |
| 740 | frequency that hardware will select. |
| 741 | |
| 742 | @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620) |
| 743 | @param EAX Lower 32-bits of MSR value. |
| 744 | Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER. |
| 745 | @param EDX Upper 32-bits of MSR value. |
| 746 | Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER. |
| 747 | |
| 748 | <b>Example usage</b> |
| 749 | @code |
| 750 | MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr; |
| 751 | |
| 752 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT); |
| 753 | AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64); |
| 754 | @endcode |
| 755 | **/ |
| 756 | #define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620 |
| 757 | |
| 758 | /** |
| 759 | MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT |
| 760 | **/ |
| 761 | typedef union { |
| 762 | /// |
| 763 | /// Individual bit fields |
| 764 | /// |
| 765 | struct { |
| 766 | /// |
| 767 | /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the |
| 768 | /// LLC/Ring. |
| 769 | /// |
| 770 | UINT32 MAX_RATIO : 7; |
| 771 | UINT32 Reserved1 : 1; |
| 772 | /// |
| 773 | /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum |
| 774 | /// possible ratio of the LLC/Ring. |
| 775 | /// |
| 776 | UINT32 MIN_RATIO : 7; |
| 777 | UINT32 Reserved2 : 17; |
| 778 | UINT32 Reserved3 : 32; |
| 779 | } Bits; |
| 780 | /// |
| 781 | /// All bit fields as a 32-bit value |
| 782 | /// |
| 783 | UINT32 Uint32; |
| 784 | /// |
| 785 | /// All bit fields as a 64-bit value |
| 786 | /// |
| 787 | UINT64 Uint64; |
| 788 | } MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER; |
| 789 | |
| 790 | /** |
| 791 | Package. Reserved (R/O) Reads return 0. |
| 792 | |
| 793 | @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639) |
| 794 | @param EAX Lower 32-bits of MSR value. |
| 795 | @param EDX Upper 32-bits of MSR value. |
| 796 | |
| 797 | <b>Example usage</b> |
| 798 | @code |
| 799 | UINT64 Msr; |
| 800 | |
| 801 | Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS); |
| 802 | @endcode |
| 803 | @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. |
| 804 | **/ |
| 805 | #define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639 |
| 806 | |
| 807 | /** |
| 808 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency |
| 809 | refers to processor core frequency). |
| 810 | |
| 811 | @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690) |
| 812 | @param EAX Lower 32-bits of MSR value. |
| 813 | Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER. |
| 814 | @param EDX Upper 32-bits of MSR value. |
| 815 | Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER. |
| 816 | |
| 817 | <b>Example usage</b> |
| 818 | @code |
| 819 | MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr; |
| 820 | |
| 821 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS); |
| 822 | AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64); |
| 823 | @endcode |
| 824 | @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. |
| 825 | **/ |
| 826 | #define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690 |
| 827 | |
| 828 | /** |
| 829 | MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS |
| 830 | **/ |
| 831 | typedef union { |
| 832 | /// |
| 833 | /// Individual bit fields |
| 834 | /// |
| 835 | struct { |
| 836 | /// |
| 837 | /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is |
| 838 | /// reduced below the operating system request due to assertion of |
| 839 | /// external PROCHOT. |
| 840 | /// |
| 841 | UINT32 PROCHOT_Status : 1; |
| 842 | /// |
| 843 | /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the |
| 844 | /// operating system request due to a thermal event. |
| 845 | /// |
| 846 | UINT32 ThermalStatus : 1; |
| 847 | /// |
| 848 | /// [Bit 2] Power Budget Management Status (R0) When set, frequency is |
| 849 | /// reduced below the operating system request due to PBM limit. |
| 850 | /// |
| 851 | UINT32 PowerBudgetManagementStatus : 1; |
| 852 | /// |
| 853 | /// [Bit 3] Platform Configuration Services Status (R0) When set, |
| 854 | /// frequency is reduced below the operating system request due to PCS |
| 855 | /// limit. |
| 856 | /// |
| 857 | UINT32 PlatformConfigurationServicesStatus : 1; |
| 858 | UINT32 Reserved1 : 1; |
| 859 | /// |
| 860 | /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) |
| 861 | /// When set, frequency is reduced below the operating system request |
| 862 | /// because the processor has detected that utilization is low. |
| 863 | /// |
| 864 | UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1; |
| 865 | /// |
| 866 | /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced |
| 867 | /// below the operating system request due to a thermal alert from the |
| 868 | /// Voltage Regulator. |
| 869 | /// |
| 870 | UINT32 VRThermAlertStatus : 1; |
| 871 | UINT32 Reserved2 : 1; |
| 872 | /// |
| 873 | /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is |
| 874 | /// reduced below the operating system request due to electrical design |
| 875 | /// point constraints (e.g. maximum electrical current consumption). |
| 876 | /// |
| 877 | UINT32 ElectricalDesignPointStatus : 1; |
| 878 | UINT32 Reserved3 : 1; |
| 879 | /// |
| 880 | /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced |
| 881 | /// below the operating system request due to Multi-Core Turbo limits. |
| 882 | /// |
| 883 | UINT32 MultiCoreTurboStatus : 1; |
| 884 | UINT32 Reserved4 : 2; |
| 885 | /// |
| 886 | /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced |
| 887 | /// below max non-turbo P1. |
| 888 | /// |
| 889 | UINT32 FrequencyP1Status : 1; |
| 890 | /// |
| 891 | /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When |
| 892 | /// set, frequency is reduced below max n-core turbo frequency. |
| 893 | /// |
| 894 | UINT32 TurboFrequencyLimitingStatus : 1; |
| 895 | /// |
| 896 | /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is |
| 897 | /// reduced below the operating system request. |
| 898 | /// |
| 899 | UINT32 FrequencyLimitingStatus : 1; |
| 900 | /// |
| 901 | /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit |
| 902 | /// has asserted since the log bit was last cleared. This log bit will |
| 903 | /// remain set until cleared by software writing 0. |
| 904 | /// |
| 905 | UINT32 PROCHOT_Log : 1; |
| 906 | /// |
| 907 | /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit |
| 908 | /// has asserted since the log bit was last cleared. This log bit will |
| 909 | /// remain set until cleared by software writing 0. |
| 910 | /// |
| 911 | UINT32 ThermalLog : 1; |
| 912 | /// |
| 913 | /// [Bit 18] Power Budget Management Log When set, indicates that the PBM |
| 914 | /// Status bit has asserted since the log bit was last cleared. This log |
| 915 | /// bit will remain set until cleared by software writing 0. |
| 916 | /// |
| 917 | UINT32 PowerBudgetManagementLog : 1; |
| 918 | /// |
| 919 | /// [Bit 19] Platform Configuration Services Log When set, indicates that |
| 920 | /// the PCS Status bit has asserted since the log bit was last cleared. |
| 921 | /// This log bit will remain set until cleared by software writing 0. |
| 922 | /// |
| 923 | UINT32 PlatformConfigurationServicesLog : 1; |
| 924 | UINT32 Reserved5 : 1; |
| 925 | /// |
| 926 | /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set, |
| 927 | /// indicates that the AUBFC Status bit has asserted since the log bit was |
| 928 | /// last cleared. This log bit will remain set until cleared by software |
| 929 | /// writing 0. |
| 930 | /// |
| 931 | UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1; |
| 932 | /// |
| 933 | /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm |
| 934 | /// Alert Status bit has asserted since the log bit was last cleared. This |
| 935 | /// log bit will remain set until cleared by software writing 0. |
| 936 | /// |
| 937 | UINT32 VRThermAlertLog : 1; |
| 938 | UINT32 Reserved6 : 1; |
| 939 | /// |
| 940 | /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP |
| 941 | /// Status bit has asserted since the log bit was last cleared. This log |
| 942 | /// bit will remain set until cleared by software writing 0. |
| 943 | /// |
| 944 | UINT32 ElectricalDesignPointLog : 1; |
| 945 | UINT32 Reserved7 : 1; |
| 946 | /// |
| 947 | /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core |
| 948 | /// Turbo Status bit has asserted since the log bit was last cleared. This |
| 949 | /// log bit will remain set until cleared by software writing 0. |
| 950 | /// |
| 951 | UINT32 MultiCoreTurboLog : 1; |
| 952 | UINT32 Reserved8 : 2; |
| 953 | /// |
| 954 | /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core |
| 955 | /// Frequency P1 Status bit has asserted since the log bit was last |
| 956 | /// cleared. This log bit will remain set until cleared by software |
| 957 | /// writing 0. |
| 958 | /// |
| 959 | UINT32 CoreFrequencyP1Log : 1; |
| 960 | /// |
| 961 | /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set, |
| 962 | /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit |
| 963 | /// has asserted since the log bit was last cleared. This log bit will |
| 964 | /// remain set until cleared by software writing 0. |
| 965 | /// |
| 966 | UINT32 TurboFrequencyLimitingLog : 1; |
| 967 | /// |
| 968 | /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core |
| 969 | /// Frequency Limiting Status bit has asserted since the log bit was last |
| 970 | /// cleared. This log bit will remain set until cleared by software |
| 971 | /// writing 0. |
| 972 | /// |
| 973 | UINT32 CoreFrequencyLimitingLog : 1; |
| 974 | UINT32 Reserved9 : 32; |
| 975 | } Bits; |
| 976 | /// |
| 977 | /// All bit fields as a 32-bit value |
| 978 | /// |
| 979 | UINT32 Uint32; |
| 980 | /// |
| 981 | /// All bit fields as a 64-bit value |
| 982 | /// |
| 983 | UINT64 Uint64; |
| 984 | } MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER; |
| 985 | |
| 986 | /** |
| 987 | THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H, |
| 988 | ECX=0):EBX.RDT-M[bit 12] = 1. |
| 989 | |
| 990 | @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D) |
| 991 | @param EAX Lower 32-bits of MSR value. |
| 992 | Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER. |
| 993 | @param EDX Upper 32-bits of MSR value. |
| 994 | Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER. |
| 995 | |
| 996 | <b>Example usage</b> |
| 997 | @code |
| 998 | MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr; |
| 999 | |
| 1000 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL); |
| 1001 | AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64); |
| 1002 | @endcode |
| 1003 | @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM. |
| 1004 | **/ |
| 1005 | #define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D |
| 1006 | |
| 1007 | /** |
| 1008 | MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL |
| 1009 | **/ |
| 1010 | typedef union { |
| 1011 | /// |
| 1012 | /// Individual bit fields |
| 1013 | /// |
| 1014 | struct { |
| 1015 | /// |
| 1016 | /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3 |
| 1017 | /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03: |
| 1018 | /// Local memory bandwidth monitoring All other encoding reserved. |
| 1019 | /// |
| 1020 | UINT32 EventID : 8; |
| 1021 | UINT32 Reserved1 : 24; |
| 1022 | /// |
| 1023 | /// [Bits 41:32] RMID (RW). |
| 1024 | /// |
| 1025 | UINT32 RMID : 10; |
| 1026 | UINT32 Reserved2 : 22; |
| 1027 | } Bits; |
| 1028 | /// |
| 1029 | /// All bit fields as a 64-bit value |
| 1030 | /// |
| 1031 | UINT64 Uint64; |
| 1032 | } MSR_XEON_D_IA32_QM_EVTSEL_REGISTER; |
| 1033 | |
| 1034 | /** |
| 1035 | THREAD. Resource Association Register (R/W). |
| 1036 | |
| 1037 | @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F) |
| 1038 | @param EAX Lower 32-bits of MSR value. |
| 1039 | Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER. |
| 1040 | @param EDX Upper 32-bits of MSR value. |
| 1041 | Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER. |
| 1042 | |
| 1043 | <b>Example usage</b> |
| 1044 | @code |
| 1045 | MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr; |
| 1046 | |
| 1047 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC); |
| 1048 | AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64); |
| 1049 | @endcode |
| 1050 | @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM. |
| 1051 | **/ |
| 1052 | #define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F |
| 1053 | |
| 1054 | /** |
| 1055 | MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC |
| 1056 | **/ |
| 1057 | typedef union { |
| 1058 | /// |
| 1059 | /// Individual bit fields |
| 1060 | /// |
| 1061 | struct { |
| 1062 | /// |
| 1063 | /// [Bits 9:0] RMID. |
| 1064 | /// |
| 1065 | UINT32 RMID : 10; |
| 1066 | UINT32 Reserved1 : 22; |
| 1067 | /// |
| 1068 | /// [Bits 51:32] COS (R/W). |
| 1069 | /// |
| 1070 | UINT32 COS : 20; |
| 1071 | UINT32 Reserved2 : 12; |
| 1072 | } Bits; |
| 1073 | /// |
| 1074 | /// All bit fields as a 64-bit value |
| 1075 | /// |
| 1076 | UINT64 Uint64; |
| 1077 | } MSR_XEON_D_IA32_PQR_ASSOC_REGISTER; |
| 1078 | |
| 1079 | /** |
| 1080 | Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H, |
| 1081 | ECX=1):EDX.COS_MAX[15:0] >= n. |
| 1082 | |
| 1083 | @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n |
| 1084 | @param EAX Lower 32-bits of MSR value. |
| 1085 | Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER. |
| 1086 | @param EDX Upper 32-bits of MSR value. |
| 1087 | Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER. |
| 1088 | |
| 1089 | <b>Example usage</b> |
| 1090 | @code |
| 1091 | MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr; |
| 1092 | |
| 1093 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0); |
| 1094 | AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64); |
| 1095 | @endcode |
| 1096 | @note MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM. |
| 1097 | MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM. |
| 1098 | MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM. |
| 1099 | MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM. |
| 1100 | MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM. |
| 1101 | MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM. |
| 1102 | MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM. |
| 1103 | MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM. |
| 1104 | MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM. |
| 1105 | MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM. |
| 1106 | MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM. |
| 1107 | MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM. |
| 1108 | MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM. |
| 1109 | MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM. |
| 1110 | MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM. |
| 1111 | MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM. |
| 1112 | @{ |
| 1113 | **/ |
| 1114 | #define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90 |
| 1115 | #define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91 |
| 1116 | #define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92 |
| 1117 | #define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93 |
| 1118 | #define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94 |
| 1119 | #define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95 |
| 1120 | #define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96 |
| 1121 | #define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97 |
| 1122 | #define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98 |
| 1123 | #define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99 |
| 1124 | #define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A |
| 1125 | #define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B |
| 1126 | #define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C |
| 1127 | #define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D |
| 1128 | #define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E |
| 1129 | #define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F |
| 1130 | /// @} |
| 1131 | |
| 1132 | /** |
| 1133 | MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0 |
| 1134 | to #MSR_XEON_D_IA32_L3_QOS_MASK_15. |
| 1135 | **/ |
| 1136 | typedef union { |
| 1137 | /// |
| 1138 | /// Individual bit fields |
| 1139 | /// |
| 1140 | struct { |
| 1141 | /// |
| 1142 | /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement. |
| 1143 | /// |
| 1144 | UINT32 CBM : 20; |
| 1145 | UINT32 Reserved2 : 12; |
| 1146 | UINT32 Reserved3 : 32; |
| 1147 | } Bits; |
| 1148 | /// |
| 1149 | /// All bit fields as a 32-bit value |
| 1150 | /// |
| 1151 | UINT32 Uint32; |
| 1152 | /// |
| 1153 | /// All bit fields as a 64-bit value |
| 1154 | /// |
| 1155 | UINT64 Uint64; |
| 1156 | } MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER; |
| 1157 | |
| 1158 | /** |
| 1159 | Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, |
| 1160 | RW if MSR_PLATFORM_INFO.[28] = 1. |
| 1161 | |
| 1162 | @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC) |
| 1163 | @param EAX Lower 32-bits of MSR value. |
| 1164 | Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER. |
| 1165 | @param EDX Upper 32-bits of MSR value. |
| 1166 | Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER. |
| 1167 | |
| 1168 | <b>Example usage</b> |
| 1169 | @code |
| 1170 | MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr; |
| 1171 | |
| 1172 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3); |
| 1173 | @endcode |
| 1174 | @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM. |
| 1175 | **/ |
| 1176 | #define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC |
| 1177 | |
| 1178 | /** |
| 1179 | MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3 |
| 1180 | **/ |
| 1181 | typedef union { |
| 1182 | /// |
| 1183 | /// Individual bit fields |
| 1184 | /// |
| 1185 | struct { |
| 1186 | UINT32 Reserved1 : 32; |
| 1187 | UINT32 Reserved2 : 31; |
| 1188 | /// |
| 1189 | /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, |
| 1190 | /// the processor uses override configuration specified in |
| 1191 | /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor |
| 1192 | /// uses factory-set configuration (Default). |
| 1193 | /// |
| 1194 | UINT32 TurboRatioLimitConfigurationSemaphore : 1; |
| 1195 | } Bits; |
| 1196 | /// |
| 1197 | /// All bit fields as a 64-bit value |
| 1198 | /// |
| 1199 | UINT64 Uint64; |
| 1200 | } MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER; |
| 1201 | |
| 1202 | /** |
| 1203 | Package. Cache Allocation Technology Configuration (R/W). |
| 1204 | |
| 1205 | @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81) |
| 1206 | @param EAX Lower 32-bits of MSR value. |
| 1207 | Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER. |
| 1208 | @param EDX Upper 32-bits of MSR value. |
| 1209 | Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER. |
| 1210 | |
| 1211 | <b>Example usage</b> |
| 1212 | @code |
| 1213 | MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr; |
| 1214 | |
| 1215 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG); |
| 1216 | AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64); |
| 1217 | @endcode |
| 1218 | @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM. |
| 1219 | **/ |
| 1220 | #define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81 |
| 1221 | |
| 1222 | /** |
| 1223 | MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG |
| 1224 | **/ |
| 1225 | typedef union { |
| 1226 | /// |
| 1227 | /// Individual bit fields |
| 1228 | /// |
| 1229 | struct { |
| 1230 | /// |
| 1231 | /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology. |
| 1232 | /// |
| 1233 | UINT32 CAT : 1; |
| 1234 | UINT32 Reserved1 : 31; |
| 1235 | UINT32 Reserved2 : 32; |
| 1236 | } Bits; |
| 1237 | /// |
| 1238 | /// All bit fields as a 32-bit value |
| 1239 | /// |
| 1240 | UINT32 Uint32; |
| 1241 | /// |
| 1242 | /// All bit fields as a 64-bit value |
| 1243 | /// |
| 1244 | UINT64 Uint64; |
| 1245 | } MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER; |
| 1246 | |
| 1247 | #endif |