Ronak Kanabar | 1ae366f | 2023-06-07 01:21:56 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | MSR Definitions for Pentium(R) 4 Processors. |
| 3 | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not |
| 7 | provided for that MSR. |
| 8 | |
| 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> |
| 10 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 11 | |
| 12 | @par Specification Reference: |
| 13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR) |
| 15 | |
| 16 | **/ |
| 17 | |
| 18 | #ifndef __PENTIUM_4_MSR_H__ |
| 19 | #define __PENTIUM_4_MSR_H__ |
| 20 | |
| 21 | #include <Register/Intel/ArchitecturalMsr.h> |
| 22 | |
| 23 | /** |
| 24 | Is Pentium(R) 4 Processors? |
| 25 | |
| 26 | @param DisplayFamily Display Family ID |
| 27 | @param DisplayModel Display Model ID |
| 28 | |
| 29 | @retval TRUE Yes, it is. |
| 30 | @retval FALSE No, it isn't. |
| 31 | **/ |
| 32 | #define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \ |
| 33 | (DisplayFamily == 0x0F \ |
| 34 | ) |
| 35 | |
| 36 | /** |
| 37 | 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range |
| 38 | Determination.". |
| 39 | |
| 40 | @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006) |
| 41 | @param EAX Lower 32-bits of MSR value. |
| 42 | @param EDX Upper 32-bits of MSR value. |
| 43 | |
| 44 | <b>Example usage</b> |
| 45 | @code |
| 46 | UINT64 Msr; |
| 47 | |
| 48 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE); |
| 49 | AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr); |
| 50 | @endcode |
| 51 | @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM. |
| 52 | **/ |
| 53 | #define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006 |
| 54 | |
| 55 | /** |
| 56 | 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W) |
| 57 | Enables and disables processor features; (R) indicates current processor |
| 58 | configuration. |
| 59 | |
| 60 | @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A) |
| 61 | @param EAX Lower 32-bits of MSR value. |
| 62 | Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER. |
| 63 | @param EDX Upper 32-bits of MSR value. |
| 64 | Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER. |
| 65 | |
| 66 | <b>Example usage</b> |
| 67 | @code |
| 68 | MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr; |
| 69 | |
| 70 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON); |
| 71 | AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64); |
| 72 | @endcode |
| 73 | @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM. |
| 74 | **/ |
| 75 | #define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A |
| 76 | |
| 77 | /** |
| 78 | MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON |
| 79 | **/ |
| 80 | typedef union { |
| 81 | /// |
| 82 | /// Individual bit fields |
| 83 | /// |
| 84 | struct { |
| 85 | /// |
| 86 | /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state |
| 87 | /// output is enabled (1) or disabled (0) as set by the strapping of SMI#. |
| 88 | /// The value in this bit is written on the deassertion of RESET#; the bit |
| 89 | /// is set to 1 when the address bus signal is asserted. |
| 90 | /// |
| 91 | UINT32 OutputTriStateEnabled : 1; |
| 92 | /// |
| 93 | /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST |
| 94 | /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The |
| 95 | /// value in this bit is written on the deassertion of RESET#; the bit is |
| 96 | /// set to 1 when the address bus signal is asserted. |
| 97 | /// |
| 98 | UINT32 ExecuteBIST : 1; |
| 99 | /// |
| 100 | /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue |
| 101 | /// depth for the system bus is 1 (1) or up to 12 (0) as set by the |
| 102 | /// strapping of A7#. The value in this bit is written on the deassertion |
| 103 | /// of RESET#; the bit is set to 1 when the address bus signal is asserted. |
| 104 | /// |
| 105 | UINT32 InOrderQueueDepth : 1; |
| 106 | /// |
| 107 | /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR# |
| 108 | /// observation is enabled (0) or disabled (1) as determined by the |
| 109 | /// strapping of A9#. The value in this bit is written on the deassertion |
| 110 | /// of RESET#; the bit is set to 1 when the address bus signal is asserted. |
| 111 | /// |
| 112 | UINT32 MCERR_ObservationDisabled : 1; |
| 113 | /// |
| 114 | /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT# |
| 115 | /// observation is enabled (0) or disabled (1) as determined by the |
| 116 | /// strapping of A10#. The value in this bit is written on the deassertion |
| 117 | /// of RESET#; the bit is set to 1 when the address bus signal is asserted. |
| 118 | /// |
| 119 | UINT32 BINIT_ObservationEnabled : 1; |
| 120 | /// |
| 121 | /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID |
| 122 | /// value as set by the strapping of A12# and A11#. The logical cluster ID |
| 123 | /// value is written into the field on the deassertion of RESET#; the |
| 124 | /// field is set to 1 when the address bus signal is asserted. |
| 125 | /// |
| 126 | UINT32 APICClusterID : 2; |
| 127 | /// |
| 128 | /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled |
| 129 | /// (0) or disabled (1) as set by the strapping of A15#. The value in this |
| 130 | /// bit is written on the deassertion of RESET#; the bit is set to 1 when |
| 131 | /// the address bus signal is asserted. |
| 132 | /// |
| 133 | UINT32 BusParkDisable : 1; |
| 134 | UINT32 Reserved1 : 4; |
| 135 | /// |
| 136 | /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set |
| 137 | /// by the strapping of BR[3:0]. The logical ID value is written into the |
| 138 | /// field on the deassertion of RESET#; the field is set to 1 when the |
| 139 | /// address bus signal is asserted. |
| 140 | /// |
| 141 | UINT32 AgentID : 2; |
| 142 | UINT32 Reserved2 : 18; |
| 143 | UINT32 Reserved3 : 32; |
| 144 | } Bits; |
| 145 | /// |
| 146 | /// All bit fields as a 32-bit value |
| 147 | /// |
| 148 | UINT32 Uint32; |
| 149 | /// |
| 150 | /// All bit fields as a 64-bit value |
| 151 | /// |
| 152 | UINT64 Uint64; |
| 153 | } MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER; |
| 154 | |
| 155 | /** |
| 156 | 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W) |
| 157 | Enables and disables processor features. |
| 158 | |
| 159 | @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B) |
| 160 | @param EAX Lower 32-bits of MSR value. |
| 161 | Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER. |
| 162 | @param EDX Upper 32-bits of MSR value. |
| 163 | Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER. |
| 164 | |
| 165 | <b>Example usage</b> |
| 166 | @code |
| 167 | MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr; |
| 168 | |
| 169 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON); |
| 170 | AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64); |
| 171 | @endcode |
| 172 | @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM. |
| 173 | **/ |
| 174 | #define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B |
| 175 | |
| 176 | /** |
| 177 | MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON |
| 178 | **/ |
| 179 | typedef union { |
| 180 | /// |
| 181 | /// Individual bit fields |
| 182 | /// |
| 183 | struct { |
| 184 | /// |
| 185 | /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the |
| 186 | /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear |
| 187 | /// to disabled (0, default). |
| 188 | /// |
| 189 | UINT32 RCNT_SCNT : 1; |
| 190 | /// |
| 191 | /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data |
| 192 | /// bus parity checking; clear to enable parity checking. |
| 193 | /// |
| 194 | UINT32 DataErrorCheckingDisable : 1; |
| 195 | /// |
| 196 | /// [Bit 2] Response Error Checking Disable (R/W) Set to disable |
| 197 | /// (default); clear to enable. |
| 198 | /// |
| 199 | UINT32 ResponseErrorCheckingDisable : 1; |
| 200 | /// |
| 201 | /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable |
| 202 | /// (default); clear to enable. |
| 203 | /// |
| 204 | UINT32 AddressRequestErrorCheckingDisable : 1; |
| 205 | /// |
| 206 | /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving |
| 207 | /// for initiator bus requests (default); clear to enable. |
| 208 | /// |
| 209 | UINT32 InitiatorMCERR_Disable : 1; |
| 210 | /// |
| 211 | /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving |
| 212 | /// for initiator internal errors (default); clear to enable. |
| 213 | /// |
| 214 | UINT32 InternalMCERR_Disable : 1; |
| 215 | /// |
| 216 | /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver |
| 217 | /// (default); clear to enable driver. |
| 218 | /// |
| 219 | UINT32 BINIT_DriverDisable : 1; |
| 220 | UINT32 Reserved1 : 25; |
| 221 | UINT32 Reserved2 : 32; |
| 222 | } Bits; |
| 223 | /// |
| 224 | /// All bit fields as a 32-bit value |
| 225 | /// |
| 226 | UINT32 Uint32; |
| 227 | /// |
| 228 | /// All bit fields as a 64-bit value |
| 229 | /// |
| 230 | UINT64 Uint64; |
| 231 | } MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER; |
| 232 | |
| 233 | /** |
| 234 | 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of |
| 235 | this MSR varies according to the MODEL value in the CPUID version |
| 236 | information. The following bit field layout applies to Pentium 4 and Xeon |
| 237 | Processors with MODEL encoding equal or greater than 2. (R) The field |
| 238 | Indicates the current processor frequency configuration. |
| 239 | |
| 240 | @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C) |
| 241 | @param EAX Lower 32-bits of MSR value. |
| 242 | Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER. |
| 243 | @param EDX Upper 32-bits of MSR value. |
| 244 | Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER. |
| 245 | |
| 246 | <b>Example usage</b> |
| 247 | @code |
| 248 | MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr; |
| 249 | |
| 250 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID); |
| 251 | @endcode |
| 252 | @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM. |
| 253 | **/ |
| 254 | #define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C |
| 255 | |
| 256 | /** |
| 257 | MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID |
| 258 | **/ |
| 259 | typedef union { |
| 260 | /// |
| 261 | /// Individual bit fields |
| 262 | /// |
| 263 | struct { |
| 264 | UINT32 Reserved1 : 16; |
| 265 | /// |
| 266 | /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable |
| 267 | /// bus speed: *EncodingScalable Bus Speed* |
| 268 | /// |
| 269 | /// 000B 100 MHz (Model 2). |
| 270 | /// 000B 266 MHz (Model 3 or 4) |
| 271 | /// 001B 133 MHz |
| 272 | /// 010B 200 MHz |
| 273 | /// 011B 166 MHz |
| 274 | /// 100B 333 MHz (Model 6) |
| 275 | /// |
| 276 | /// 133.33 MHz should be utilized if performing calculation with System |
| 277 | /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if |
| 278 | /// performing calculation with System Bus Speed when encoding is 011B. |
| 279 | /// 266.67 MHz should be utilized if performing calculation with System |
| 280 | /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33 |
| 281 | /// MHz should be utilized if performing calculation with System Bus |
| 282 | /// Speed when encoding is 100B and model encoding = 6. All other values |
| 283 | /// are reserved. |
| 284 | /// |
| 285 | UINT32 ScalableBusSpeed : 3; |
| 286 | UINT32 Reserved2 : 5; |
| 287 | /// |
| 288 | /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R) |
| 289 | /// The processor core clock frequency to system bus frequency ratio |
| 290 | /// observed at the de-assertion of the reset pin. |
| 291 | /// |
| 292 | UINT32 ClockRatio : 8; |
| 293 | UINT32 Reserved3 : 32; |
| 294 | } Bits; |
| 295 | /// |
| 296 | /// All bit fields as a 32-bit value |
| 297 | /// |
| 298 | UINT32 Uint32; |
| 299 | /// |
| 300 | /// All bit fields as a 64-bit value |
| 301 | /// |
| 302 | UINT64 Uint64; |
| 303 | } MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER; |
| 304 | |
| 305 | /** |
| 306 | 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of |
| 307 | this MSR varies according to the MODEL value of the CPUID version |
| 308 | information. This bit field layout applies to Pentium 4 and Xeon Processors |
| 309 | with MODEL encoding less than 2. Indicates current processor frequency |
| 310 | configuration. |
| 311 | |
| 312 | @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C) |
| 313 | @param EAX Lower 32-bits of MSR value. |
| 314 | Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER. |
| 315 | @param EDX Upper 32-bits of MSR value. |
| 316 | Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER. |
| 317 | |
| 318 | <b>Example usage</b> |
| 319 | @code |
| 320 | MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr; |
| 321 | |
| 322 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1); |
| 323 | @endcode |
| 324 | @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM. |
| 325 | **/ |
| 326 | #define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C |
| 327 | |
| 328 | /** |
| 329 | MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 |
| 330 | **/ |
| 331 | typedef union { |
| 332 | /// |
| 333 | /// Individual bit fields |
| 334 | /// |
| 335 | struct { |
| 336 | UINT32 Reserved1 : 21; |
| 337 | /// |
| 338 | /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable |
| 339 | /// bus speed: *Encoding* *Scalable Bus Speed* |
| 340 | /// |
| 341 | /// 000B 100 MHz All others values reserved. |
| 342 | /// |
| 343 | UINT32 ScalableBusSpeed : 3; |
| 344 | UINT32 Reserved2 : 8; |
| 345 | UINT32 Reserved3 : 32; |
| 346 | } Bits; |
| 347 | /// |
| 348 | /// All bit fields as a 32-bit value |
| 349 | /// |
| 350 | UINT32 Uint32; |
| 351 | /// |
| 352 | /// All bit fields as a 64-bit value |
| 353 | /// |
| 354 | UINT64 Uint64; |
| 355 | } MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER; |
| 356 | |
| 357 | /** |
| 358 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section |
| 359 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register |
| 360 | state at time of machine check error. When in non-64-bit modes at the time |
| 361 | of the error, bits 63-32 do not contain valid data. |
| 362 | |
| 363 | @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180) |
| 364 | @param EAX Lower 32-bits of MSR value. |
| 365 | @param EDX Upper 32-bits of MSR value. |
| 366 | |
| 367 | <b>Example usage</b> |
| 368 | @code |
| 369 | UINT64 Msr; |
| 370 | |
| 371 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX); |
| 372 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr); |
| 373 | @endcode |
| 374 | @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM. |
| 375 | **/ |
| 376 | #define MSR_PENTIUM_4_MCG_RAX 0x00000180 |
| 377 | |
| 378 | /** |
| 379 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section |
| 380 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register |
| 381 | state at time of machine check error. When in non-64-bit modes at the time |
| 382 | of the error, bits 63-32 do not contain valid data. |
| 383 | |
| 384 | @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181) |
| 385 | @param EAX Lower 32-bits of MSR value. |
| 386 | @param EDX Upper 32-bits of MSR value. |
| 387 | |
| 388 | <b>Example usage</b> |
| 389 | @code |
| 390 | UINT64 Msr; |
| 391 | |
| 392 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX); |
| 393 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr); |
| 394 | @endcode |
| 395 | @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM. |
| 396 | **/ |
| 397 | #define MSR_PENTIUM_4_MCG_RBX 0x00000181 |
| 398 | |
| 399 | /** |
| 400 | 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section |
| 401 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register |
| 402 | state at time of machine check error. When in non-64-bit modes at the time |
| 403 | of the error, bits 63-32 do not contain valid data. |
| 404 | |
| 405 | @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182) |
| 406 | @param EAX Lower 32-bits of MSR value. |
| 407 | @param EDX Upper 32-bits of MSR value. |
| 408 | |
| 409 | <b>Example usage</b> |
| 410 | @code |
| 411 | UINT64 Msr; |
| 412 | |
| 413 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX); |
| 414 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr); |
| 415 | @endcode |
| 416 | @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM. |
| 417 | **/ |
| 418 | #define MSR_PENTIUM_4_MCG_RCX 0x00000182 |
| 419 | |
| 420 | /** |
| 421 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section |
| 422 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register |
| 423 | state at time of machine check error. When in non-64-bit modes at the time |
| 424 | of the error, bits 63-32 do not contain valid data. |
| 425 | |
| 426 | @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183) |
| 427 | @param EAX Lower 32-bits of MSR value. |
| 428 | @param EDX Upper 32-bits of MSR value. |
| 429 | |
| 430 | <b>Example usage</b> |
| 431 | @code |
| 432 | UINT64 Msr; |
| 433 | |
| 434 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX); |
| 435 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr); |
| 436 | @endcode |
| 437 | @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM. |
| 438 | **/ |
| 439 | #define MSR_PENTIUM_4_MCG_RDX 0x00000183 |
| 440 | |
| 441 | /** |
| 442 | 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section |
| 443 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register |
| 444 | state at time of machine check error. When in non-64-bit modes at the time |
| 445 | of the error, bits 63-32 do not contain valid data. |
| 446 | |
| 447 | @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184) |
| 448 | @param EAX Lower 32-bits of MSR value. |
| 449 | @param EDX Upper 32-bits of MSR value. |
| 450 | |
| 451 | <b>Example usage</b> |
| 452 | @code |
| 453 | UINT64 Msr; |
| 454 | |
| 455 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI); |
| 456 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr); |
| 457 | @endcode |
| 458 | @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM. |
| 459 | **/ |
| 460 | #define MSR_PENTIUM_4_MCG_RSI 0x00000184 |
| 461 | |
| 462 | /** |
| 463 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section |
| 464 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register |
| 465 | state at time of machine check error. When in non-64-bit modes at the time |
| 466 | of the error, bits 63-32 do not contain valid data. |
| 467 | |
| 468 | @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185) |
| 469 | @param EAX Lower 32-bits of MSR value. |
| 470 | @param EDX Upper 32-bits of MSR value. |
| 471 | |
| 472 | <b>Example usage</b> |
| 473 | @code |
| 474 | UINT64 Msr; |
| 475 | |
| 476 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI); |
| 477 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr); |
| 478 | @endcode |
| 479 | @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM. |
| 480 | **/ |
| 481 | #define MSR_PENTIUM_4_MCG_RDI 0x00000185 |
| 482 | |
| 483 | /** |
| 484 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section |
| 485 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register |
| 486 | state at time of machine check error. When in non-64-bit modes at the time |
| 487 | of the error, bits 63-32 do not contain valid data. |
| 488 | |
| 489 | @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186) |
| 490 | @param EAX Lower 32-bits of MSR value. |
| 491 | @param EDX Upper 32-bits of MSR value. |
| 492 | |
| 493 | <b>Example usage</b> |
| 494 | @code |
| 495 | UINT64 Msr; |
| 496 | |
| 497 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP); |
| 498 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr); |
| 499 | @endcode |
| 500 | @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM. |
| 501 | **/ |
| 502 | #define MSR_PENTIUM_4_MCG_RBP 0x00000186 |
| 503 | |
| 504 | /** |
| 505 | 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section |
| 506 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register |
| 507 | state at time of machine check error. When in non-64-bit modes at the time |
| 508 | of the error, bits 63-32 do not contain valid data. |
| 509 | |
| 510 | @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187) |
| 511 | @param EAX Lower 32-bits of MSR value. |
| 512 | @param EDX Upper 32-bits of MSR value. |
| 513 | |
| 514 | <b>Example usage</b> |
| 515 | @code |
| 516 | UINT64 Msr; |
| 517 | |
| 518 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP); |
| 519 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr); |
| 520 | @endcode |
| 521 | @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM. |
| 522 | **/ |
| 523 | #define MSR_PENTIUM_4_MCG_RSP 0x00000187 |
| 524 | |
| 525 | /** |
| 526 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section |
| 527 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register |
| 528 | state at time of machine check error. When in non-64-bit modes at the time |
| 529 | of the error, bits 63-32 do not contain valid data. |
| 530 | |
| 531 | @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188) |
| 532 | @param EAX Lower 32-bits of MSR value. |
| 533 | @param EDX Upper 32-bits of MSR value. |
| 534 | |
| 535 | <b>Example usage</b> |
| 536 | @code |
| 537 | UINT64 Msr; |
| 538 | |
| 539 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS); |
| 540 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr); |
| 541 | @endcode |
| 542 | @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM. |
| 543 | **/ |
| 544 | #define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188 |
| 545 | |
| 546 | /** |
| 547 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section |
| 548 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register |
| 549 | state at time of machine check error. When in non-64-bit modes at the time |
| 550 | of the error, bits 63-32 do not contain valid data. |
| 551 | |
| 552 | @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189) |
| 553 | @param EAX Lower 32-bits of MSR value. |
| 554 | @param EDX Upper 32-bits of MSR value. |
| 555 | |
| 556 | <b>Example usage</b> |
| 557 | @code |
| 558 | UINT64 Msr; |
| 559 | |
| 560 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP); |
| 561 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr); |
| 562 | @endcode |
| 563 | @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM. |
| 564 | **/ |
| 565 | #define MSR_PENTIUM_4_MCG_RIP 0x00000189 |
| 566 | |
| 567 | /** |
| 568 | 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6, |
| 569 | "IA32_MCG Extended Machine Check State MSRs.". |
| 570 | |
| 571 | @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A) |
| 572 | @param EAX Lower 32-bits of MSR value. |
| 573 | Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER. |
| 574 | @param EDX Upper 32-bits of MSR value. |
| 575 | Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER. |
| 576 | |
| 577 | <b>Example usage</b> |
| 578 | @code |
| 579 | MSR_PENTIUM_4_MCG_MISC_REGISTER Msr; |
| 580 | |
| 581 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC); |
| 582 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64); |
| 583 | @endcode |
| 584 | @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM. |
| 585 | **/ |
| 586 | #define MSR_PENTIUM_4_MCG_MISC 0x0000018A |
| 587 | |
| 588 | /** |
| 589 | MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC |
| 590 | **/ |
| 591 | typedef union { |
| 592 | /// |
| 593 | /// Individual bit fields |
| 594 | /// |
| 595 | struct { |
| 596 | /// |
| 597 | /// [Bit 0] DS When set, the bit indicates that a page assist or page |
| 598 | /// fault occurred during DS normal operation. The processors response is |
| 599 | /// to shut down. The bit is used as an aid for debugging DS handling |
| 600 | /// code. It is the responsibility of the user (BIOS or operating system) |
| 601 | /// to clear this bit for normal operation. |
| 602 | /// |
| 603 | UINT32 DS : 1; |
| 604 | UINT32 Reserved1 : 31; |
| 605 | UINT32 Reserved2 : 32; |
| 606 | } Bits; |
| 607 | /// |
| 608 | /// All bit fields as a 32-bit value |
| 609 | /// |
| 610 | UINT32 Uint32; |
| 611 | /// |
| 612 | /// All bit fields as a 64-bit value |
| 613 | /// |
| 614 | UINT64 Uint64; |
| 615 | } MSR_PENTIUM_4_MCG_MISC_REGISTER; |
| 616 | |
| 617 | /** |
| 618 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG |
| 619 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated |
| 620 | state-save MSRs) exist only in Intel 64 processors. These registers contain |
| 621 | valid information only when the processor is operating in 64-bit mode at the |
| 622 | time of the error. |
| 623 | |
| 624 | @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190) |
| 625 | @param EAX Lower 32-bits of MSR value. |
| 626 | @param EDX Upper 32-bits of MSR value. |
| 627 | |
| 628 | <b>Example usage</b> |
| 629 | @code |
| 630 | UINT64 Msr; |
| 631 | |
| 632 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8); |
| 633 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr); |
| 634 | @endcode |
| 635 | @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM. |
| 636 | **/ |
| 637 | #define MSR_PENTIUM_4_MCG_R8 0x00000190 |
| 638 | |
| 639 | /** |
| 640 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6, |
| 641 | "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the |
| 642 | associated state-save MSRs) exist only in Intel 64 processors. These |
| 643 | registers contain valid information only when the processor is operating in |
| 644 | 64-bit mode at the time of the error. |
| 645 | |
| 646 | @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191) |
| 647 | @param EAX Lower 32-bits of MSR value. |
| 648 | @param EDX Upper 32-bits of MSR value. |
| 649 | |
| 650 | <b>Example usage</b> |
| 651 | @code |
| 652 | UINT64 Msr; |
| 653 | |
| 654 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9); |
| 655 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr); |
| 656 | @endcode |
| 657 | @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM. |
| 658 | **/ |
| 659 | #define MSR_PENTIUM_4_MCG_R9 0x00000191 |
| 660 | |
| 661 | /** |
| 662 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG |
| 663 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated |
| 664 | state-save MSRs) exist only in Intel 64 processors. These registers contain |
| 665 | valid information only when the processor is operating in 64-bit mode at the |
| 666 | time of the error. |
| 667 | |
| 668 | @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192) |
| 669 | @param EAX Lower 32-bits of MSR value. |
| 670 | @param EDX Upper 32-bits of MSR value. |
| 671 | |
| 672 | <b>Example usage</b> |
| 673 | @code |
| 674 | UINT64 Msr; |
| 675 | |
| 676 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10); |
| 677 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr); |
| 678 | @endcode |
| 679 | @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM. |
| 680 | **/ |
| 681 | #define MSR_PENTIUM_4_MCG_R10 0x00000192 |
| 682 | |
| 683 | /** |
| 684 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG |
| 685 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated |
| 686 | state-save MSRs) exist only in Intel 64 processors. These registers contain |
| 687 | valid information only when the processor is operating in 64-bit mode at the |
| 688 | time of the error. |
| 689 | |
| 690 | @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193) |
| 691 | @param EAX Lower 32-bits of MSR value. |
| 692 | @param EDX Upper 32-bits of MSR value. |
| 693 | |
| 694 | <b>Example usage</b> |
| 695 | @code |
| 696 | UINT64 Msr; |
| 697 | |
| 698 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11); |
| 699 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr); |
| 700 | @endcode |
| 701 | @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM. |
| 702 | **/ |
| 703 | #define MSR_PENTIUM_4_MCG_R11 0x00000193 |
| 704 | |
| 705 | /** |
| 706 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG |
| 707 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated |
| 708 | state-save MSRs) exist only in Intel 64 processors. These registers contain |
| 709 | valid information only when the processor is operating in 64-bit mode at the |
| 710 | time of the error. |
| 711 | |
| 712 | @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194) |
| 713 | @param EAX Lower 32-bits of MSR value. |
| 714 | @param EDX Upper 32-bits of MSR value. |
| 715 | |
| 716 | <b>Example usage</b> |
| 717 | @code |
| 718 | UINT64 Msr; |
| 719 | |
| 720 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12); |
| 721 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr); |
| 722 | @endcode |
| 723 | @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM. |
| 724 | **/ |
| 725 | #define MSR_PENTIUM_4_MCG_R12 0x00000194 |
| 726 | |
| 727 | /** |
| 728 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG |
| 729 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated |
| 730 | state-save MSRs) exist only in Intel 64 processors. These registers contain |
| 731 | valid information only when the processor is operating in 64-bit mode at the |
| 732 | time of the error. |
| 733 | |
| 734 | @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195) |
| 735 | @param EAX Lower 32-bits of MSR value. |
| 736 | @param EDX Upper 32-bits of MSR value. |
| 737 | |
| 738 | <b>Example usage</b> |
| 739 | @code |
| 740 | UINT64 Msr; |
| 741 | |
| 742 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13); |
| 743 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr); |
| 744 | @endcode |
| 745 | @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM. |
| 746 | **/ |
| 747 | #define MSR_PENTIUM_4_MCG_R13 0x00000195 |
| 748 | |
| 749 | /** |
| 750 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG |
| 751 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated |
| 752 | state-save MSRs) exist only in Intel 64 processors. These registers contain |
| 753 | valid information only when the processor is operating in 64-bit mode at the |
| 754 | time of the error. |
| 755 | |
| 756 | @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196) |
| 757 | @param EAX Lower 32-bits of MSR value. |
| 758 | @param EDX Upper 32-bits of MSR value. |
| 759 | |
| 760 | <b>Example usage</b> |
| 761 | @code |
| 762 | UINT64 Msr; |
| 763 | |
| 764 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14); |
| 765 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr); |
| 766 | @endcode |
| 767 | @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM. |
| 768 | **/ |
| 769 | #define MSR_PENTIUM_4_MCG_R14 0x00000196 |
| 770 | |
| 771 | /** |
| 772 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG |
| 773 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated |
| 774 | state-save MSRs) exist only in Intel 64 processors. These registers contain |
| 775 | valid information only when the processor is operating in 64-bit mode at the |
| 776 | time of the error. |
| 777 | |
| 778 | @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197) |
| 779 | @param EAX Lower 32-bits of MSR value. |
| 780 | @param EDX Upper 32-bits of MSR value. |
| 781 | |
| 782 | <b>Example usage</b> |
| 783 | @code |
| 784 | UINT64 Msr; |
| 785 | |
| 786 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15); |
| 787 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr); |
| 788 | @endcode |
| 789 | @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM. |
| 790 | **/ |
| 791 | #define MSR_PENTIUM_4_MCG_R15 0x00000197 |
| 792 | |
| 793 | /** |
| 794 | Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors: |
| 795 | When read, specifies the value of the target TM2 transition last written. |
| 796 | When set, it sets the next target value for TM2 transition. 4, 6. Shared. |
| 797 | For Family F, Model 4 and Model 6 processors: When read, specifies the value |
| 798 | of the target TM2 transition last written. Writes may cause #GP exceptions. |
| 799 | |
| 800 | @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D) |
| 801 | @param EAX Lower 32-bits of MSR value. |
| 802 | @param EDX Upper 32-bits of MSR value. |
| 803 | |
| 804 | <b>Example usage</b> |
| 805 | @code |
| 806 | UINT64 Msr; |
| 807 | |
| 808 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL); |
| 809 | AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr); |
| 810 | @endcode |
| 811 | @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM. |
| 812 | **/ |
| 813 | #define MSR_PENTIUM_4_THERM2_CTL 0x0000019D |
| 814 | |
| 815 | /** |
| 816 | 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W). |
| 817 | |
| 818 | @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0) |
| 819 | @param EAX Lower 32-bits of MSR value. |
| 820 | Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER. |
| 821 | @param EDX Upper 32-bits of MSR value. |
| 822 | Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER. |
| 823 | |
| 824 | <b>Example usage</b> |
| 825 | @code |
| 826 | MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr; |
| 827 | |
| 828 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE); |
| 829 | AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64); |
| 830 | @endcode |
| 831 | @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM. |
| 832 | **/ |
| 833 | #define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0 |
| 834 | |
| 835 | /** |
| 836 | MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE |
| 837 | **/ |
| 838 | typedef union { |
| 839 | /// |
| 840 | /// Individual bit fields |
| 841 | /// |
| 842 | struct { |
| 843 | /// |
| 844 | /// [Bit 0] Fast-Strings Enable. See Table 2-2. |
| 845 | /// |
| 846 | UINT32 FastStrings : 1; |
| 847 | UINT32 Reserved1 : 1; |
| 848 | /// |
| 849 | /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable. |
| 850 | /// |
| 851 | UINT32 FPU : 1; |
| 852 | /// |
| 853 | /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal |
| 854 | /// Monitor," and see Table 2-2. |
| 855 | /// |
| 856 | UINT32 TM1 : 1; |
| 857 | /// |
| 858 | /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception |
| 859 | /// to be issued instead of a split-lock cycle. Operating systems that set |
| 860 | /// this bit must align system structures to avoid split-lock scenarios. |
| 861 | /// When the bit is clear (default), normal split-locks are issued to the |
| 862 | /// bus. |
| 863 | /// This debug feature is specific to the Pentium 4 processor. |
| 864 | /// |
| 865 | UINT32 SplitLockDisable : 1; |
| 866 | UINT32 Reserved2 : 1; |
| 867 | /// |
| 868 | /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level |
| 869 | /// cache is disabled; when clear (default) the third-level cache is |
| 870 | /// enabled. This flag is reserved for processors that do not have a |
| 871 | /// third-level cache. Note that the bit controls only the third-level |
| 872 | /// cache; and only if overall caching is enabled through the CD flag of |
| 873 | /// control register CR0, the page-level cache controls, and/or the MTRRs. |
| 874 | /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.". |
| 875 | /// |
| 876 | UINT32 ThirdLevelCacheDisable : 1; |
| 877 | /// |
| 878 | /// [Bit 7] Performance Monitoring Available (R) See Table 2-2. |
| 879 | /// |
| 880 | UINT32 PerformanceMonitoring : 1; |
| 881 | /// |
| 882 | /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is |
| 883 | /// suppressed during a Split Lock access. When clear (default), LOCK is |
| 884 | /// not suppressed. |
| 885 | /// |
| 886 | UINT32 SuppressLockEnable : 1; |
| 887 | /// |
| 888 | /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue. |
| 889 | /// When clear (default), enables the prefetch queue. |
| 890 | /// |
| 891 | UINT32 PrefetchQueueDisable : 1; |
| 892 | /// |
| 893 | /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt |
| 894 | /// reporting through the FERR# pin is enabled; when clear, this interrupt |
| 895 | /// reporting function is disabled. |
| 896 | /// When this flag is set and the processor is in the stop-clock state |
| 897 | /// (STPCLK# is asserted), asserting the FERR# pin signals to the |
| 898 | /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI, |
| 899 | /// SMI#, or RESET#) is pending and that the processor should return to |
| 900 | /// normal operation to handle the interrupt. This flag does not affect |
| 901 | /// the normal operation of the FERR# pin (to indicate an unmasked |
| 902 | /// floatingpoint error) when the STPCLK# pin is not asserted. |
| 903 | /// |
| 904 | UINT32 FERR : 1; |
| 905 | /// |
| 906 | /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See |
| 907 | /// Table 2-2. When set, the processor does not support branch trace |
| 908 | /// storage (BTS); when clear, BTS is supported. |
| 909 | /// |
| 910 | UINT32 BTS : 1; |
| 911 | /// |
| 912 | /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable |
| 913 | /// (R) See Table 2-2. When set, the processor does not support processor |
| 914 | /// event-based sampling (PEBS); when clear, PEBS is supported. |
| 915 | /// |
| 916 | UINT32 PEBS : 1; |
| 917 | /// |
| 918 | /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal |
| 919 | /// sensor indicates that the die temperature is at the predetermined |
| 920 | /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce |
| 921 | /// the bus to core ratio and voltage according to the value last written |
| 922 | /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the |
| 923 | /// processor does not change the VID signals or the bus to core ratio |
| 924 | /// when the processor enters a thermal managed state. If the TM2 feature |
| 925 | /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then |
| 926 | /// this feature is not supported and BIOS must not alter the contents of |
| 927 | /// this bit location. The processor is operating out of spec if both this |
| 928 | /// bit and the TM1 bit are set to disabled states. |
| 929 | /// |
| 930 | UINT32 TM2 : 1; |
| 931 | UINT32 Reserved3 : 4; |
| 932 | /// |
| 933 | /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2. |
| 934 | /// |
| 935 | UINT32 MONITOR : 1; |
| 936 | /// |
| 937 | /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1, |
| 938 | /// the processor fetches the cache line of the 128-byte sector containing |
| 939 | /// currently required data. When set to 0, the processor fetches both |
| 940 | /// cache lines in the sector. |
| 941 | /// Single processor platforms should not set this bit. Server platforms |
| 942 | /// should set or clear this bit based on platform performance observed |
| 943 | /// in validation and testing. BIOS may contain a setup option that |
| 944 | /// controls the setting of this bit. |
| 945 | /// |
| 946 | UINT32 AdjacentCacheLinePrefetchDisable : 1; |
| 947 | UINT32 Reserved4 : 2; |
| 948 | /// |
| 949 | /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this |
| 950 | /// can cause unexpected behavior to software that depends on the |
| 951 | /// availability of CPUID leaves greater than 3. |
| 952 | /// |
| 953 | UINT32 LimitCpuidMaxval : 1; |
| 954 | /// |
| 955 | /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2. |
| 956 | /// |
| 957 | UINT32 xTPR_Message_Disable : 1; |
| 958 | /// |
| 959 | /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache |
| 960 | /// is placed in shared mode; when clear (default), the cache is placed in |
| 961 | /// adaptive mode. This bit is only enabled for IA-32 processors that |
| 962 | /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data |
| 963 | /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are |
| 964 | /// identical, data in L1 is shared across logical processors. Otherwise, |
| 965 | /// L1 is not shared and cache use is competitive. If the Context ID |
| 966 | /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1, |
| 967 | /// the ability to switch modes is not supported. BIOS must not alter the |
| 968 | /// contents of IA32_MISC_ENABLE[24]. |
| 969 | /// |
| 970 | UINT32 L1DataCacheContextMode : 1; |
| 971 | UINT32 Reserved5 : 7; |
| 972 | UINT32 Reserved6 : 2; |
| 973 | /// |
| 974 | /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2. |
| 975 | /// |
| 976 | UINT32 XD : 1; |
| 977 | UINT32 Reserved7 : 29; |
| 978 | } Bits; |
| 979 | /// |
| 980 | /// All bit fields as a 64-bit value |
| 981 | /// |
| 982 | UINT64 Uint64; |
| 983 | } MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER; |
| 984 | |
| 985 | /** |
| 986 | 3, 4, 6. Shared. Platform Feature Requirements (R). |
| 987 | |
| 988 | @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1) |
| 989 | @param EAX Lower 32-bits of MSR value. |
| 990 | Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER. |
| 991 | @param EDX Upper 32-bits of MSR value. |
| 992 | Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER. |
| 993 | |
| 994 | <b>Example usage</b> |
| 995 | @code |
| 996 | MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr; |
| 997 | |
| 998 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV); |
| 999 | @endcode |
| 1000 | @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM. |
| 1001 | **/ |
| 1002 | #define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1 |
| 1003 | |
| 1004 | /** |
| 1005 | MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV |
| 1006 | **/ |
| 1007 | typedef union { |
| 1008 | /// |
| 1009 | /// Individual bit fields |
| 1010 | /// |
| 1011 | struct { |
| 1012 | UINT32 Reserved1 : 18; |
| 1013 | /// |
| 1014 | /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor |
| 1015 | /// has specific platform requirements. The details of the platform |
| 1016 | /// requirements are listed in the respective data sheets of the processor. |
| 1017 | /// |
| 1018 | UINT32 PLATFORM : 1; |
| 1019 | UINT32 Reserved2 : 13; |
| 1020 | UINT32 Reserved3 : 32; |
| 1021 | } Bits; |
| 1022 | /// |
| 1023 | /// All bit fields as a 32-bit value |
| 1024 | /// |
| 1025 | UINT32 Uint32; |
| 1026 | /// |
| 1027 | /// All bit fields as a 64-bit value |
| 1028 | /// |
| 1029 | UINT64 Uint64; |
| 1030 | } MSR_PENTIUM_4_PLATFORM_BRV_REGISTER; |
| 1031 | |
| 1032 | /** |
| 1033 | 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains |
| 1034 | a pointer to the last branch instruction that the processor executed prior |
| 1035 | to the last exception that was generated or the last interrupt that was |
| 1036 | handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear |
| 1037 | IP Linear address of the last branch instruction (If IA-32e mode is active). |
| 1038 | From Linear IP Linear address of the last branch instruction. Reserved. |
| 1039 | |
| 1040 | @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7) |
| 1041 | @param EAX Lower 32-bits of MSR value. |
| 1042 | @param EDX Upper 32-bits of MSR value. |
| 1043 | |
| 1044 | <b>Example usage</b> |
| 1045 | @code |
| 1046 | UINT64 Msr; |
| 1047 | |
| 1048 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP); |
| 1049 | @endcode |
| 1050 | @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM. |
| 1051 | **/ |
| 1052 | #define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7 |
| 1053 | |
| 1054 | /** |
| 1055 | 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area |
| 1056 | contains a pointer to the target of the last branch instruction that the |
| 1057 | processor executed prior to the last exception that was generated or the |
| 1058 | last interrupt that was handled. See Section 17.13.3, "Last Exception |
| 1059 | Records.". Unique. From Linear IP Linear address of the target of the last |
| 1060 | branch instruction (If IA-32e mode is active). From Linear IP Linear address |
| 1061 | of the target of the last branch instruction. Reserved. |
| 1062 | |
| 1063 | @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8) |
| 1064 | @param EAX Lower 32-bits of MSR value. |
| 1065 | @param EDX Upper 32-bits of MSR value. |
| 1066 | |
| 1067 | <b>Example usage</b> |
| 1068 | @code |
| 1069 | UINT64 Msr; |
| 1070 | |
| 1071 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP); |
| 1072 | @endcode |
| 1073 | @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM. |
| 1074 | **/ |
| 1075 | #define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8 |
| 1076 | |
| 1077 | /** |
| 1078 | 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug |
| 1079 | features are used. Bit definitions are discussed in the referenced section. |
| 1080 | See Section 17.13.1, "MSR_DEBUGCTLA MSR.". |
| 1081 | |
| 1082 | @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9) |
| 1083 | @param EAX Lower 32-bits of MSR value. |
| 1084 | @param EDX Upper 32-bits of MSR value. |
| 1085 | |
| 1086 | <b>Example usage</b> |
| 1087 | @code |
| 1088 | UINT64 Msr; |
| 1089 | |
| 1090 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA); |
| 1091 | AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr); |
| 1092 | @endcode |
| 1093 | @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM. |
| 1094 | **/ |
| 1095 | #define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9 |
| 1096 | |
| 1097 | /** |
| 1098 | 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an |
| 1099 | index (0-3 or 0-15) that points to the top of the last branch record stack |
| 1100 | (that is, that points the index of the MSR containing the most recent branch |
| 1101 | record). See Section 17.13.2, "LBR Stack for Processors Based on Intel |
| 1102 | NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH. |
| 1103 | |
| 1104 | @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA) |
| 1105 | @param EAX Lower 32-bits of MSR value. |
| 1106 | @param EDX Upper 32-bits of MSR value. |
| 1107 | |
| 1108 | <b>Example usage</b> |
| 1109 | @code |
| 1110 | UINT64 Msr; |
| 1111 | |
| 1112 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS); |
| 1113 | AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr); |
| 1114 | @endcode |
| 1115 | @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. |
| 1116 | **/ |
| 1117 | #define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA |
| 1118 | |
| 1119 | /** |
| 1120 | 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record |
| 1121 | registers on the last branch record stack. It contains pointers to the |
| 1122 | source and destination instruction for one of the last four branches, |
| 1123 | exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through |
| 1124 | MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models |
| 1125 | 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See |
| 1126 | Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording |
| 1127 | for Processors based on Skylake Microarchitecture.". |
| 1128 | |
| 1129 | @param ECX MSR_PENTIUM_4_LASTBRANCH_n |
| 1130 | @param EAX Lower 32-bits of MSR value. |
| 1131 | @param EDX Upper 32-bits of MSR value. |
| 1132 | |
| 1133 | <b>Example usage</b> |
| 1134 | @code |
| 1135 | UINT64 Msr; |
| 1136 | |
| 1137 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0); |
| 1138 | AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr); |
| 1139 | @endcode |
| 1140 | @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM. |
| 1141 | MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM. |
| 1142 | MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM. |
| 1143 | MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM. |
| 1144 | @{ |
| 1145 | **/ |
| 1146 | #define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB |
| 1147 | #define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC |
| 1148 | #define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD |
| 1149 | #define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE |
| 1150 | /// @} |
| 1151 | |
| 1152 | /** |
| 1153 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.". |
| 1154 | |
| 1155 | @param ECX MSR_PENTIUM_4_BPU_COUNTERn |
| 1156 | @param EAX Lower 32-bits of MSR value. |
| 1157 | @param EDX Upper 32-bits of MSR value. |
| 1158 | |
| 1159 | <b>Example usage</b> |
| 1160 | @code |
| 1161 | UINT64 Msr; |
| 1162 | |
| 1163 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0); |
| 1164 | AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr); |
| 1165 | @endcode |
| 1166 | @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM. |
| 1167 | MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM. |
| 1168 | MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM. |
| 1169 | MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM. |
| 1170 | @{ |
| 1171 | **/ |
| 1172 | #define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300 |
| 1173 | #define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301 |
| 1174 | #define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302 |
| 1175 | #define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303 |
| 1176 | /// @} |
| 1177 | |
| 1178 | /** |
| 1179 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.". |
| 1180 | |
| 1181 | @param ECX MSR_PENTIUM_4_MS_COUNTERn |
| 1182 | @param EAX Lower 32-bits of MSR value. |
| 1183 | @param EDX Upper 32-bits of MSR value. |
| 1184 | |
| 1185 | <b>Example usage</b> |
| 1186 | @code |
| 1187 | UINT64 Msr; |
| 1188 | |
| 1189 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0); |
| 1190 | AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr); |
| 1191 | @endcode |
| 1192 | @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM. |
| 1193 | MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM. |
| 1194 | MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM. |
| 1195 | MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM. |
| 1196 | @{ |
| 1197 | **/ |
| 1198 | #define MSR_PENTIUM_4_MS_COUNTER0 0x00000304 |
| 1199 | #define MSR_PENTIUM_4_MS_COUNTER1 0x00000305 |
| 1200 | #define MSR_PENTIUM_4_MS_COUNTER2 0x00000306 |
| 1201 | #define MSR_PENTIUM_4_MS_COUNTER3 0x00000307 |
| 1202 | /// @} |
| 1203 | |
| 1204 | /** |
| 1205 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.". |
| 1206 | |
| 1207 | @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308) |
| 1208 | @param EAX Lower 32-bits of MSR value. |
| 1209 | @param EDX Upper 32-bits of MSR value. |
| 1210 | |
| 1211 | <b>Example usage</b> |
| 1212 | @code |
| 1213 | UINT64 Msr; |
| 1214 | |
| 1215 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0); |
| 1216 | AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr); |
| 1217 | @endcode |
| 1218 | @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM. |
| 1219 | MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM. |
| 1220 | MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM. |
| 1221 | MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM. |
| 1222 | @{ |
| 1223 | **/ |
| 1224 | #define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308 |
| 1225 | #define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309 |
| 1226 | #define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A |
| 1227 | #define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B |
| 1228 | /// @} |
| 1229 | |
| 1230 | /** |
| 1231 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.". |
| 1232 | |
| 1233 | @param ECX MSR_PENTIUM_4_IQ_COUNTERn |
| 1234 | @param EAX Lower 32-bits of MSR value. |
| 1235 | @param EDX Upper 32-bits of MSR value. |
| 1236 | |
| 1237 | <b>Example usage</b> |
| 1238 | @code |
| 1239 | UINT64 Msr; |
| 1240 | |
| 1241 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0); |
| 1242 | AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr); |
| 1243 | @endcode |
| 1244 | @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM. |
| 1245 | MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM. |
| 1246 | MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM. |
| 1247 | MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM. |
| 1248 | MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM. |
| 1249 | MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM. |
| 1250 | @{ |
| 1251 | **/ |
| 1252 | #define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C |
| 1253 | #define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D |
| 1254 | #define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E |
| 1255 | #define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F |
| 1256 | #define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310 |
| 1257 | #define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311 |
| 1258 | /// @} |
| 1259 | |
| 1260 | /** |
| 1261 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.". |
| 1262 | |
| 1263 | @param ECX MSR_PENTIUM_4_BPU_CCCRn |
| 1264 | @param EAX Lower 32-bits of MSR value. |
| 1265 | @param EDX Upper 32-bits of MSR value. |
| 1266 | |
| 1267 | <b>Example usage</b> |
| 1268 | @code |
| 1269 | UINT64 Msr; |
| 1270 | |
| 1271 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0); |
| 1272 | AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr); |
| 1273 | @endcode |
| 1274 | @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM. |
| 1275 | MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM. |
| 1276 | MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM. |
| 1277 | MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM. |
| 1278 | @{ |
| 1279 | **/ |
| 1280 | #define MSR_PENTIUM_4_BPU_CCCR0 0x00000360 |
| 1281 | #define MSR_PENTIUM_4_BPU_CCCR1 0x00000361 |
| 1282 | #define MSR_PENTIUM_4_BPU_CCCR2 0x00000362 |
| 1283 | #define MSR_PENTIUM_4_BPU_CCCR3 0x00000363 |
| 1284 | /// @} |
| 1285 | |
| 1286 | /** |
| 1287 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.". |
| 1288 | |
| 1289 | @param ECX MSR_PENTIUM_4_MS_CCCRn |
| 1290 | @param EAX Lower 32-bits of MSR value. |
| 1291 | @param EDX Upper 32-bits of MSR value. |
| 1292 | |
| 1293 | <b>Example usage</b> |
| 1294 | @code |
| 1295 | UINT64 Msr; |
| 1296 | |
| 1297 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0); |
| 1298 | AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr); |
| 1299 | @endcode |
| 1300 | @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM. |
| 1301 | MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM. |
| 1302 | MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM. |
| 1303 | MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM. |
| 1304 | @{ |
| 1305 | **/ |
| 1306 | #define MSR_PENTIUM_4_MS_CCCR0 0x00000364 |
| 1307 | #define MSR_PENTIUM_4_MS_CCCR1 0x00000365 |
| 1308 | #define MSR_PENTIUM_4_MS_CCCR2 0x00000366 |
| 1309 | #define MSR_PENTIUM_4_MS_CCCR3 0x00000367 |
| 1310 | /// @} |
| 1311 | |
| 1312 | /** |
| 1313 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.". |
| 1314 | |
| 1315 | @param ECX MSR_PENTIUM_4_FLAME_CCCRn |
| 1316 | @param EAX Lower 32-bits of MSR value. |
| 1317 | @param EDX Upper 32-bits of MSR value. |
| 1318 | |
| 1319 | <b>Example usage</b> |
| 1320 | @code |
| 1321 | UINT64 Msr; |
| 1322 | |
| 1323 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0); |
| 1324 | AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr); |
| 1325 | @endcode |
| 1326 | @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM. |
| 1327 | MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM. |
| 1328 | MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM. |
| 1329 | MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM. |
| 1330 | @{ |
| 1331 | **/ |
| 1332 | #define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368 |
| 1333 | #define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369 |
| 1334 | #define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A |
| 1335 | #define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B |
| 1336 | /// @} |
| 1337 | |
| 1338 | /** |
| 1339 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.". |
| 1340 | |
| 1341 | @param ECX MSR_PENTIUM_4_IQ_CCCRn |
| 1342 | @param EAX Lower 32-bits of MSR value. |
| 1343 | @param EDX Upper 32-bits of MSR value. |
| 1344 | |
| 1345 | <b>Example usage</b> |
| 1346 | @code |
| 1347 | UINT64 Msr; |
| 1348 | |
| 1349 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0); |
| 1350 | AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr); |
| 1351 | @endcode |
| 1352 | @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM. |
| 1353 | MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM. |
| 1354 | MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM. |
| 1355 | MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM. |
| 1356 | MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM. |
| 1357 | MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM. |
| 1358 | @{ |
| 1359 | **/ |
| 1360 | #define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C |
| 1361 | #define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D |
| 1362 | #define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E |
| 1363 | #define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F |
| 1364 | #define MSR_PENTIUM_4_IQ_CCCR4 0x00000370 |
| 1365 | #define MSR_PENTIUM_4_IQ_CCCR5 0x00000371 |
| 1366 | /// @} |
| 1367 | |
| 1368 | /** |
| 1369 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1370 | |
| 1371 | @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0) |
| 1372 | @param EAX Lower 32-bits of MSR value. |
| 1373 | @param EDX Upper 32-bits of MSR value. |
| 1374 | |
| 1375 | <b>Example usage</b> |
| 1376 | @code |
| 1377 | UINT64 Msr; |
| 1378 | |
| 1379 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0); |
| 1380 | AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr); |
| 1381 | @endcode |
| 1382 | @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM. |
| 1383 | **/ |
| 1384 | #define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0 |
| 1385 | |
| 1386 | /** |
| 1387 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1388 | |
| 1389 | @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1) |
| 1390 | @param EAX Lower 32-bits of MSR value. |
| 1391 | @param EDX Upper 32-bits of MSR value. |
| 1392 | |
| 1393 | <b>Example usage</b> |
| 1394 | @code |
| 1395 | UINT64 Msr; |
| 1396 | |
| 1397 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1); |
| 1398 | AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr); |
| 1399 | @endcode |
| 1400 | @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM. |
| 1401 | **/ |
| 1402 | #define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1 |
| 1403 | |
| 1404 | /** |
| 1405 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1406 | |
| 1407 | @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2) |
| 1408 | @param EAX Lower 32-bits of MSR value. |
| 1409 | @param EDX Upper 32-bits of MSR value. |
| 1410 | |
| 1411 | <b>Example usage</b> |
| 1412 | @code |
| 1413 | UINT64 Msr; |
| 1414 | |
| 1415 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0); |
| 1416 | AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr); |
| 1417 | @endcode |
| 1418 | @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM. |
| 1419 | **/ |
| 1420 | #define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2 |
| 1421 | |
| 1422 | /** |
| 1423 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1424 | |
| 1425 | @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3) |
| 1426 | @param EAX Lower 32-bits of MSR value. |
| 1427 | @param EDX Upper 32-bits of MSR value. |
| 1428 | |
| 1429 | <b>Example usage</b> |
| 1430 | @code |
| 1431 | UINT64 Msr; |
| 1432 | |
| 1433 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1); |
| 1434 | AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr); |
| 1435 | @endcode |
| 1436 | @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM. |
| 1437 | **/ |
| 1438 | #define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3 |
| 1439 | |
| 1440 | /** |
| 1441 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1442 | |
| 1443 | @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4) |
| 1444 | @param EAX Lower 32-bits of MSR value. |
| 1445 | @param EDX Upper 32-bits of MSR value. |
| 1446 | |
| 1447 | <b>Example usage</b> |
| 1448 | @code |
| 1449 | UINT64 Msr; |
| 1450 | |
| 1451 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0); |
| 1452 | AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr); |
| 1453 | @endcode |
| 1454 | @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM. |
| 1455 | **/ |
| 1456 | #define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4 |
| 1457 | |
| 1458 | /** |
| 1459 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1460 | |
| 1461 | @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5) |
| 1462 | @param EAX Lower 32-bits of MSR value. |
| 1463 | @param EDX Upper 32-bits of MSR value. |
| 1464 | |
| 1465 | <b>Example usage</b> |
| 1466 | @code |
| 1467 | UINT64 Msr; |
| 1468 | |
| 1469 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1); |
| 1470 | AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr); |
| 1471 | @endcode |
| 1472 | @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM. |
| 1473 | **/ |
| 1474 | #define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5 |
| 1475 | |
| 1476 | /** |
| 1477 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1478 | |
| 1479 | @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6) |
| 1480 | @param EAX Lower 32-bits of MSR value. |
| 1481 | @param EDX Upper 32-bits of MSR value. |
| 1482 | |
| 1483 | <b>Example usage</b> |
| 1484 | @code |
| 1485 | UINT64 Msr; |
| 1486 | |
| 1487 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0); |
| 1488 | AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr); |
| 1489 | @endcode |
| 1490 | @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM. |
| 1491 | **/ |
| 1492 | #define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6 |
| 1493 | |
| 1494 | /** |
| 1495 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1496 | |
| 1497 | @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7) |
| 1498 | @param EAX Lower 32-bits of MSR value. |
| 1499 | @param EDX Upper 32-bits of MSR value. |
| 1500 | |
| 1501 | <b>Example usage</b> |
| 1502 | @code |
| 1503 | UINT64 Msr; |
| 1504 | |
| 1505 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1); |
| 1506 | AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr); |
| 1507 | @endcode |
| 1508 | @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM. |
| 1509 | **/ |
| 1510 | #define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7 |
| 1511 | |
| 1512 | /** |
| 1513 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1514 | |
| 1515 | @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8) |
| 1516 | @param EAX Lower 32-bits of MSR value. |
| 1517 | @param EDX Upper 32-bits of MSR value. |
| 1518 | |
| 1519 | <b>Example usage</b> |
| 1520 | @code |
| 1521 | UINT64 Msr; |
| 1522 | |
| 1523 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0); |
| 1524 | AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr); |
| 1525 | @endcode |
| 1526 | @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM. |
| 1527 | **/ |
| 1528 | #define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8 |
| 1529 | |
| 1530 | /** |
| 1531 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1532 | |
| 1533 | @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9) |
| 1534 | @param EAX Lower 32-bits of MSR value. |
| 1535 | @param EDX Upper 32-bits of MSR value. |
| 1536 | |
| 1537 | <b>Example usage</b> |
| 1538 | @code |
| 1539 | UINT64 Msr; |
| 1540 | |
| 1541 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1); |
| 1542 | AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr); |
| 1543 | @endcode |
| 1544 | @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM. |
| 1545 | **/ |
| 1546 | #define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9 |
| 1547 | |
| 1548 | /** |
| 1549 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1550 | |
| 1551 | @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA) |
| 1552 | @param EAX Lower 32-bits of MSR value. |
| 1553 | @param EDX Upper 32-bits of MSR value. |
| 1554 | |
| 1555 | <b>Example usage</b> |
| 1556 | @code |
| 1557 | UINT64 Msr; |
| 1558 | |
| 1559 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0); |
| 1560 | AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr); |
| 1561 | @endcode |
| 1562 | @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM. |
| 1563 | **/ |
| 1564 | #define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA |
| 1565 | |
| 1566 | /** |
| 1567 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1568 | |
| 1569 | @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB) |
| 1570 | @param EAX Lower 32-bits of MSR value. |
| 1571 | @param EDX Upper 32-bits of MSR value. |
| 1572 | |
| 1573 | <b>Example usage</b> |
| 1574 | @code |
| 1575 | UINT64 Msr; |
| 1576 | |
| 1577 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1); |
| 1578 | AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr); |
| 1579 | @endcode |
| 1580 | @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM. |
| 1581 | **/ |
| 1582 | #define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB |
| 1583 | |
| 1584 | /** |
| 1585 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1586 | |
| 1587 | @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC) |
| 1588 | @param EAX Lower 32-bits of MSR value. |
| 1589 | @param EDX Upper 32-bits of MSR value. |
| 1590 | |
| 1591 | <b>Example usage</b> |
| 1592 | @code |
| 1593 | UINT64 Msr; |
| 1594 | |
| 1595 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0); |
| 1596 | AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr); |
| 1597 | @endcode |
| 1598 | @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM. |
| 1599 | **/ |
| 1600 | #define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC |
| 1601 | |
| 1602 | /** |
| 1603 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1604 | |
| 1605 | @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD) |
| 1606 | @param EAX Lower 32-bits of MSR value. |
| 1607 | @param EDX Upper 32-bits of MSR value. |
| 1608 | |
| 1609 | <b>Example usage</b> |
| 1610 | @code |
| 1611 | UINT64 Msr; |
| 1612 | |
| 1613 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1); |
| 1614 | AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr); |
| 1615 | @endcode |
| 1616 | @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM. |
| 1617 | **/ |
| 1618 | #define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD |
| 1619 | |
| 1620 | /** |
| 1621 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1622 | |
| 1623 | @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE) |
| 1624 | @param EAX Lower 32-bits of MSR value. |
| 1625 | @param EDX Upper 32-bits of MSR value. |
| 1626 | |
| 1627 | <b>Example usage</b> |
| 1628 | @code |
| 1629 | UINT64 Msr; |
| 1630 | |
| 1631 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0); |
| 1632 | AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr); |
| 1633 | @endcode |
| 1634 | @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM. |
| 1635 | **/ |
| 1636 | #define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE |
| 1637 | |
| 1638 | /** |
| 1639 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1640 | |
| 1641 | @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF) |
| 1642 | @param EAX Lower 32-bits of MSR value. |
| 1643 | @param EDX Upper 32-bits of MSR value. |
| 1644 | |
| 1645 | <b>Example usage</b> |
| 1646 | @code |
| 1647 | UINT64 Msr; |
| 1648 | |
| 1649 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1); |
| 1650 | AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr); |
| 1651 | @endcode |
| 1652 | @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM. |
| 1653 | **/ |
| 1654 | #define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF |
| 1655 | |
| 1656 | /** |
| 1657 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1658 | |
| 1659 | @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0) |
| 1660 | @param EAX Lower 32-bits of MSR value. |
| 1661 | @param EDX Upper 32-bits of MSR value. |
| 1662 | |
| 1663 | <b>Example usage</b> |
| 1664 | @code |
| 1665 | UINT64 Msr; |
| 1666 | |
| 1667 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0); |
| 1668 | AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr); |
| 1669 | @endcode |
| 1670 | @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM. |
| 1671 | **/ |
| 1672 | #define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0 |
| 1673 | |
| 1674 | /** |
| 1675 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1676 | |
| 1677 | @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1) |
| 1678 | @param EAX Lower 32-bits of MSR value. |
| 1679 | @param EDX Upper 32-bits of MSR value. |
| 1680 | |
| 1681 | <b>Example usage</b> |
| 1682 | @code |
| 1683 | UINT64 Msr; |
| 1684 | |
| 1685 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1); |
| 1686 | AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr); |
| 1687 | @endcode |
| 1688 | @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM. |
| 1689 | **/ |
| 1690 | #define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1 |
| 1691 | |
| 1692 | /** |
| 1693 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1694 | |
| 1695 | @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2) |
| 1696 | @param EAX Lower 32-bits of MSR value. |
| 1697 | @param EDX Upper 32-bits of MSR value. |
| 1698 | |
| 1699 | <b>Example usage</b> |
| 1700 | @code |
| 1701 | UINT64 Msr; |
| 1702 | |
| 1703 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0); |
| 1704 | AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr); |
| 1705 | @endcode |
| 1706 | @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM. |
| 1707 | **/ |
| 1708 | #define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2 |
| 1709 | |
| 1710 | /** |
| 1711 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1712 | |
| 1713 | @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3) |
| 1714 | @param EAX Lower 32-bits of MSR value. |
| 1715 | @param EDX Upper 32-bits of MSR value. |
| 1716 | |
| 1717 | <b>Example usage</b> |
| 1718 | @code |
| 1719 | UINT64 Msr; |
| 1720 | |
| 1721 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1); |
| 1722 | AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr); |
| 1723 | @endcode |
| 1724 | @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM. |
| 1725 | **/ |
| 1726 | #define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3 |
| 1727 | |
| 1728 | /** |
| 1729 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1730 | |
| 1731 | @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4) |
| 1732 | @param EAX Lower 32-bits of MSR value. |
| 1733 | @param EDX Upper 32-bits of MSR value. |
| 1734 | |
| 1735 | <b>Example usage</b> |
| 1736 | @code |
| 1737 | UINT64 Msr; |
| 1738 | |
| 1739 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0); |
| 1740 | AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr); |
| 1741 | @endcode |
| 1742 | @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM. |
| 1743 | **/ |
| 1744 | #define MSR_PENTIUM_4_IS_ESCR0 0x000003B4 |
| 1745 | |
| 1746 | /** |
| 1747 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1748 | |
| 1749 | @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5) |
| 1750 | @param EAX Lower 32-bits of MSR value. |
| 1751 | @param EDX Upper 32-bits of MSR value. |
| 1752 | |
| 1753 | <b>Example usage</b> |
| 1754 | @code |
| 1755 | UINT64 Msr; |
| 1756 | |
| 1757 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1); |
| 1758 | AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr); |
| 1759 | @endcode |
| 1760 | @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM. |
| 1761 | **/ |
| 1762 | #define MSR_PENTIUM_4_IS_ESCR1 0x000003B5 |
| 1763 | |
| 1764 | /** |
| 1765 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1766 | |
| 1767 | @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6) |
| 1768 | @param EAX Lower 32-bits of MSR value. |
| 1769 | @param EDX Upper 32-bits of MSR value. |
| 1770 | |
| 1771 | <b>Example usage</b> |
| 1772 | @code |
| 1773 | UINT64 Msr; |
| 1774 | |
| 1775 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0); |
| 1776 | AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr); |
| 1777 | @endcode |
| 1778 | @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM. |
| 1779 | **/ |
| 1780 | #define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6 |
| 1781 | |
| 1782 | /** |
| 1783 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1784 | |
| 1785 | @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7) |
| 1786 | @param EAX Lower 32-bits of MSR value. |
| 1787 | @param EDX Upper 32-bits of MSR value. |
| 1788 | |
| 1789 | <b>Example usage</b> |
| 1790 | @code |
| 1791 | UINT64 Msr; |
| 1792 | |
| 1793 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1); |
| 1794 | AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr); |
| 1795 | @endcode |
| 1796 | @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM. |
| 1797 | **/ |
| 1798 | #define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7 |
| 1799 | |
| 1800 | /** |
| 1801 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1802 | |
| 1803 | @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8) |
| 1804 | @param EAX Lower 32-bits of MSR value. |
| 1805 | @param EDX Upper 32-bits of MSR value. |
| 1806 | |
| 1807 | <b>Example usage</b> |
| 1808 | @code |
| 1809 | UINT64 Msr; |
| 1810 | |
| 1811 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0); |
| 1812 | AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr); |
| 1813 | @endcode |
| 1814 | @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM. |
| 1815 | **/ |
| 1816 | #define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8 |
| 1817 | |
| 1818 | /** |
| 1819 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1820 | |
| 1821 | @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9) |
| 1822 | @param EAX Lower 32-bits of MSR value. |
| 1823 | @param EDX Upper 32-bits of MSR value. |
| 1824 | |
| 1825 | <b>Example usage</b> |
| 1826 | @code |
| 1827 | UINT64 Msr; |
| 1828 | |
| 1829 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1); |
| 1830 | AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr); |
| 1831 | @endcode |
| 1832 | @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM. |
| 1833 | **/ |
| 1834 | #define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9 |
| 1835 | |
| 1836 | /** |
| 1837 | 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not |
| 1838 | available on later processors. It is only available on processor family 0FH, |
| 1839 | models 01H-02H. |
| 1840 | |
| 1841 | @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA) |
| 1842 | @param EAX Lower 32-bits of MSR value. |
| 1843 | @param EDX Upper 32-bits of MSR value. |
| 1844 | |
| 1845 | <b>Example usage</b> |
| 1846 | @code |
| 1847 | UINT64 Msr; |
| 1848 | |
| 1849 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0); |
| 1850 | AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr); |
| 1851 | @endcode |
| 1852 | @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM. |
| 1853 | **/ |
| 1854 | #define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA |
| 1855 | |
| 1856 | /** |
| 1857 | 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not |
| 1858 | available on later processors. It is only available on processor family 0FH, |
| 1859 | models 01H-02H. |
| 1860 | |
| 1861 | @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB) |
| 1862 | @param EAX Lower 32-bits of MSR value. |
| 1863 | @param EDX Upper 32-bits of MSR value. |
| 1864 | |
| 1865 | <b>Example usage</b> |
| 1866 | @code |
| 1867 | UINT64 Msr; |
| 1868 | |
| 1869 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1); |
| 1870 | AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr); |
| 1871 | @endcode |
| 1872 | @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM. |
| 1873 | **/ |
| 1874 | #define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB |
| 1875 | |
| 1876 | /** |
| 1877 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1878 | |
| 1879 | @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC) |
| 1880 | @param EAX Lower 32-bits of MSR value. |
| 1881 | @param EDX Upper 32-bits of MSR value. |
| 1882 | |
| 1883 | <b>Example usage</b> |
| 1884 | @code |
| 1885 | UINT64 Msr; |
| 1886 | |
| 1887 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0); |
| 1888 | AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr); |
| 1889 | @endcode |
| 1890 | @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM. |
| 1891 | **/ |
| 1892 | #define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC |
| 1893 | |
| 1894 | /** |
| 1895 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1896 | |
| 1897 | @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD) |
| 1898 | @param EAX Lower 32-bits of MSR value. |
| 1899 | @param EDX Upper 32-bits of MSR value. |
| 1900 | |
| 1901 | <b>Example usage</b> |
| 1902 | @code |
| 1903 | UINT64 Msr; |
| 1904 | |
| 1905 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1); |
| 1906 | AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr); |
| 1907 | @endcode |
| 1908 | @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM. |
| 1909 | **/ |
| 1910 | #define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD |
| 1911 | |
| 1912 | /** |
| 1913 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1914 | |
| 1915 | @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE) |
| 1916 | @param EAX Lower 32-bits of MSR value. |
| 1917 | @param EDX Upper 32-bits of MSR value. |
| 1918 | |
| 1919 | <b>Example usage</b> |
| 1920 | @code |
| 1921 | UINT64 Msr; |
| 1922 | |
| 1923 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0); |
| 1924 | AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr); |
| 1925 | @endcode |
| 1926 | @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM. |
| 1927 | **/ |
| 1928 | #define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE |
| 1929 | |
| 1930 | /** |
| 1931 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1932 | |
| 1933 | @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0) |
| 1934 | @param EAX Lower 32-bits of MSR value. |
| 1935 | @param EDX Upper 32-bits of MSR value. |
| 1936 | |
| 1937 | <b>Example usage</b> |
| 1938 | @code |
| 1939 | UINT64 Msr; |
| 1940 | |
| 1941 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0); |
| 1942 | AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr); |
| 1943 | @endcode |
| 1944 | @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM. |
| 1945 | **/ |
| 1946 | #define MSR_PENTIUM_4_MS_ESCR0 0x000003C0 |
| 1947 | |
| 1948 | /** |
| 1949 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1950 | |
| 1951 | @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1) |
| 1952 | @param EAX Lower 32-bits of MSR value. |
| 1953 | @param EDX Upper 32-bits of MSR value. |
| 1954 | |
| 1955 | <b>Example usage</b> |
| 1956 | @code |
| 1957 | UINT64 Msr; |
| 1958 | |
| 1959 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1); |
| 1960 | AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr); |
| 1961 | @endcode |
| 1962 | @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM. |
| 1963 | **/ |
| 1964 | #define MSR_PENTIUM_4_MS_ESCR1 0x000003C1 |
| 1965 | |
| 1966 | /** |
| 1967 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1968 | |
| 1969 | @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2) |
| 1970 | @param EAX Lower 32-bits of MSR value. |
| 1971 | @param EDX Upper 32-bits of MSR value. |
| 1972 | |
| 1973 | <b>Example usage</b> |
| 1974 | @code |
| 1975 | UINT64 Msr; |
| 1976 | |
| 1977 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0); |
| 1978 | AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr); |
| 1979 | @endcode |
| 1980 | @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM. |
| 1981 | **/ |
| 1982 | #define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2 |
| 1983 | |
| 1984 | /** |
| 1985 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 1986 | |
| 1987 | @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3) |
| 1988 | @param EAX Lower 32-bits of MSR value. |
| 1989 | @param EDX Upper 32-bits of MSR value. |
| 1990 | |
| 1991 | <b>Example usage</b> |
| 1992 | @code |
| 1993 | UINT64 Msr; |
| 1994 | |
| 1995 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1); |
| 1996 | AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr); |
| 1997 | @endcode |
| 1998 | @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM. |
| 1999 | **/ |
| 2000 | #define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3 |
| 2001 | |
| 2002 | /** |
| 2003 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 2004 | |
| 2005 | @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4) |
| 2006 | @param EAX Lower 32-bits of MSR value. |
| 2007 | @param EDX Upper 32-bits of MSR value. |
| 2008 | |
| 2009 | <b>Example usage</b> |
| 2010 | @code |
| 2011 | UINT64 Msr; |
| 2012 | |
| 2013 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0); |
| 2014 | AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr); |
| 2015 | @endcode |
| 2016 | @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM. |
| 2017 | **/ |
| 2018 | #define MSR_PENTIUM_4_TC_ESCR0 0x000003C4 |
| 2019 | |
| 2020 | /** |
| 2021 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 2022 | |
| 2023 | @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5) |
| 2024 | @param EAX Lower 32-bits of MSR value. |
| 2025 | @param EDX Upper 32-bits of MSR value. |
| 2026 | |
| 2027 | <b>Example usage</b> |
| 2028 | @code |
| 2029 | UINT64 Msr; |
| 2030 | |
| 2031 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1); |
| 2032 | AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr); |
| 2033 | @endcode |
| 2034 | @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM. |
| 2035 | **/ |
| 2036 | #define MSR_PENTIUM_4_TC_ESCR1 0x000003C5 |
| 2037 | |
| 2038 | /** |
| 2039 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 2040 | |
| 2041 | @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8) |
| 2042 | @param EAX Lower 32-bits of MSR value. |
| 2043 | @param EDX Upper 32-bits of MSR value. |
| 2044 | |
| 2045 | <b>Example usage</b> |
| 2046 | @code |
| 2047 | UINT64 Msr; |
| 2048 | |
| 2049 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0); |
| 2050 | AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr); |
| 2051 | @endcode |
| 2052 | @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM. |
| 2053 | **/ |
| 2054 | #define MSR_PENTIUM_4_IX_ESCR0 0x000003C8 |
| 2055 | |
| 2056 | /** |
| 2057 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 2058 | |
| 2059 | @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9) |
| 2060 | @param EAX Lower 32-bits of MSR value. |
| 2061 | @param EDX Upper 32-bits of MSR value. |
| 2062 | |
| 2063 | <b>Example usage</b> |
| 2064 | @code |
| 2065 | UINT64 Msr; |
| 2066 | |
| 2067 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1); |
| 2068 | AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr); |
| 2069 | @endcode |
| 2070 | @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM. |
| 2071 | **/ |
| 2072 | #define MSR_PENTIUM_4_IX_ESCR1 0x000003C9 |
| 2073 | |
| 2074 | /** |
| 2075 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 2076 | |
| 2077 | @param ECX MSR_PENTIUM_4_ALF_ESCRn |
| 2078 | @param EAX Lower 32-bits of MSR value. |
| 2079 | @param EDX Upper 32-bits of MSR value. |
| 2080 | |
| 2081 | <b>Example usage</b> |
| 2082 | @code |
| 2083 | UINT64 Msr; |
| 2084 | |
| 2085 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0); |
| 2086 | AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr); |
| 2087 | @endcode |
| 2088 | @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM. |
| 2089 | MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM. |
| 2090 | MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM. |
| 2091 | MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM. |
| 2092 | MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM. |
| 2093 | MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM. |
| 2094 | @{ |
| 2095 | **/ |
| 2096 | #define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA |
| 2097 | #define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB |
| 2098 | #define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC |
| 2099 | #define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD |
| 2100 | #define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0 |
| 2101 | #define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1 |
| 2102 | /// @} |
| 2103 | |
| 2104 | /** |
| 2105 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.". |
| 2106 | |
| 2107 | @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0) |
| 2108 | @param EAX Lower 32-bits of MSR value. |
| 2109 | @param EDX Upper 32-bits of MSR value. |
| 2110 | |
| 2111 | <b>Example usage</b> |
| 2112 | @code |
| 2113 | UINT64 Msr; |
| 2114 | |
| 2115 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT); |
| 2116 | AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr); |
| 2117 | @endcode |
| 2118 | @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM. |
| 2119 | **/ |
| 2120 | #define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0 |
| 2121 | |
| 2122 | /** |
| 2123 | 0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W) |
| 2124 | Controls the enabling of processor event sampling and replay tagging. |
| 2125 | |
| 2126 | @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1) |
| 2127 | @param EAX Lower 32-bits of MSR value. |
| 2128 | Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER. |
| 2129 | @param EDX Upper 32-bits of MSR value. |
| 2130 | Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER. |
| 2131 | |
| 2132 | <b>Example usage</b> |
| 2133 | @code |
| 2134 | MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr; |
| 2135 | |
| 2136 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE); |
| 2137 | AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64); |
| 2138 | @endcode |
| 2139 | @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM. |
| 2140 | **/ |
| 2141 | #define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1 |
| 2142 | |
| 2143 | /** |
| 2144 | MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE |
| 2145 | **/ |
| 2146 | typedef union { |
| 2147 | /// |
| 2148 | /// Individual bit fields |
| 2149 | /// |
| 2150 | struct { |
| 2151 | /// |
| 2152 | /// [Bits 12:0] See Table 19-36. |
| 2153 | /// |
| 2154 | UINT32 EventNum : 13; |
| 2155 | UINT32 Reserved1 : 11; |
| 2156 | /// |
| 2157 | /// [Bit 24] UOP Tag Enables replay tagging when set. |
| 2158 | /// |
| 2159 | UINT32 UOP : 1; |
| 2160 | /// |
| 2161 | /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical |
| 2162 | /// processor when set; disables PEBS when clear (default). See Section |
| 2163 | /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target |
| 2164 | /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors |
| 2165 | /// that do not support Intel HyperThreading Technology. |
| 2166 | /// |
| 2167 | UINT32 ENABLE_PEBS_MY_THR : 1; |
| 2168 | /// |
| 2169 | /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical |
| 2170 | /// processor when set; disables PEBS when clear (default). See Section |
| 2171 | /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target |
| 2172 | /// logical processor. This bit is reserved for IA-32 processors that do |
| 2173 | /// not support Intel Hyper-Threading Technology. |
| 2174 | /// |
| 2175 | UINT32 ENABLE_PEBS_OTH_THR : 1; |
| 2176 | UINT32 Reserved2 : 5; |
| 2177 | UINT32 Reserved3 : 32; |
| 2178 | } Bits; |
| 2179 | /// |
| 2180 | /// All bit fields as a 32-bit value |
| 2181 | /// |
| 2182 | UINT32 Uint32; |
| 2183 | /// |
| 2184 | /// All bit fields as a 64-bit value |
| 2185 | /// |
| 2186 | UINT64 Uint64; |
| 2187 | } MSR_PENTIUM_4_PEBS_ENABLE_REGISTER; |
| 2188 | |
| 2189 | /** |
| 2190 | 0, 1, 2, 3, 4, 6. Shared. See Table 19-36. |
| 2191 | |
| 2192 | @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2) |
| 2193 | @param EAX Lower 32-bits of MSR value. |
| 2194 | @param EDX Upper 32-bits of MSR value. |
| 2195 | |
| 2196 | <b>Example usage</b> |
| 2197 | @code |
| 2198 | UINT64 Msr; |
| 2199 | |
| 2200 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT); |
| 2201 | AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr); |
| 2202 | @endcode |
| 2203 | @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM. |
| 2204 | **/ |
| 2205 | #define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2 |
| 2206 | |
| 2207 | /** |
| 2208 | 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch |
| 2209 | record registers on the last branch record stack (680H-68FH). This part of |
| 2210 | the stack contains pointers to the source instruction for one of the last 16 |
| 2211 | branches, exceptions, or interrupts taken by the processor. The MSRs at |
| 2212 | 680H-68FH, 6C0H-6CfH are not available in processor releases before family |
| 2213 | 0FH, model 03H. These MSRs replace MSRs previously located at |
| 2214 | 1DBH-1DEH.which performed the same function for early releases. See Section |
| 2215 | 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for |
| 2216 | Processors based on Skylake Microarchitecture.". |
| 2217 | |
| 2218 | @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP |
| 2219 | @param EAX Lower 32-bits of MSR value. |
| 2220 | @param EDX Upper 32-bits of MSR value. |
| 2221 | |
| 2222 | <b>Example usage</b> |
| 2223 | @code |
| 2224 | UINT64 Msr; |
| 2225 | |
| 2226 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP); |
| 2227 | AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr); |
| 2228 | @endcode |
| 2229 | @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM. |
| 2230 | MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM. |
| 2231 | MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM. |
| 2232 | MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM. |
| 2233 | MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM. |
| 2234 | MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM. |
| 2235 | MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM. |
| 2236 | MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM. |
| 2237 | MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM. |
| 2238 | MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM. |
| 2239 | MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM. |
| 2240 | MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM. |
| 2241 | MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM. |
| 2242 | MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM. |
| 2243 | MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM. |
| 2244 | MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM. |
| 2245 | @{ |
| 2246 | **/ |
| 2247 | #define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680 |
| 2248 | #define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681 |
| 2249 | #define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682 |
| 2250 | #define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683 |
| 2251 | #define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684 |
| 2252 | #define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685 |
| 2253 | #define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686 |
| 2254 | #define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687 |
| 2255 | #define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688 |
| 2256 | #define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689 |
| 2257 | #define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A |
| 2258 | #define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B |
| 2259 | #define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C |
| 2260 | #define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D |
| 2261 | #define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E |
| 2262 | #define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F |
| 2263 | /// @} |
| 2264 | |
| 2265 | /** |
| 2266 | 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch |
| 2267 | record registers on the last branch record stack (6C0H-6CFH). This part of |
| 2268 | the stack contains pointers to the destination instruction for one of the |
| 2269 | last 16 branches, exceptions, or interrupts that the processor took. See |
| 2270 | Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording |
| 2271 | for Processors based on Skylake Microarchitecture.". |
| 2272 | |
| 2273 | @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP |
| 2274 | @param EAX Lower 32-bits of MSR value. |
| 2275 | @param EDX Upper 32-bits of MSR value. |
| 2276 | |
| 2277 | <b>Example usage</b> |
| 2278 | @code |
| 2279 | UINT64 Msr; |
| 2280 | |
| 2281 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP); |
| 2282 | AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr); |
| 2283 | @endcode |
| 2284 | @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM. |
| 2285 | MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM. |
| 2286 | MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM. |
| 2287 | MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM. |
| 2288 | MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM. |
| 2289 | MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM. |
| 2290 | MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM. |
| 2291 | MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM. |
| 2292 | MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM. |
| 2293 | MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM. |
| 2294 | MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM. |
| 2295 | MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM. |
| 2296 | MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM. |
| 2297 | MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM. |
| 2298 | MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM. |
| 2299 | MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM. |
| 2300 | @{ |
| 2301 | **/ |
| 2302 | #define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0 |
| 2303 | #define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1 |
| 2304 | #define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2 |
| 2305 | #define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3 |
| 2306 | #define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4 |
| 2307 | #define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5 |
| 2308 | #define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6 |
| 2309 | #define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7 |
| 2310 | #define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8 |
| 2311 | #define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9 |
| 2312 | #define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA |
| 2313 | #define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB |
| 2314 | #define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC |
| 2315 | #define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD |
| 2316 | #define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE |
| 2317 | #define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF |
| 2318 | /// @} |
| 2319 | |
| 2320 | /** |
| 2321 | 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section |
| 2322 | 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to |
| 2323 | 8-MByte L3 Cache.". |
| 2324 | |
| 2325 | @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC) |
| 2326 | @param EAX Lower 32-bits of MSR value. |
| 2327 | @param EDX Upper 32-bits of MSR value. |
| 2328 | |
| 2329 | <b>Example usage</b> |
| 2330 | @code |
| 2331 | UINT64 Msr; |
| 2332 | |
| 2333 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0); |
| 2334 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr); |
| 2335 | @endcode |
| 2336 | @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM. |
| 2337 | **/ |
| 2338 | #define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC |
| 2339 | |
| 2340 | /** |
| 2341 | 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W). |
| 2342 | |
| 2343 | @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD) |
| 2344 | @param EAX Lower 32-bits of MSR value. |
| 2345 | @param EDX Upper 32-bits of MSR value. |
| 2346 | |
| 2347 | <b>Example usage</b> |
| 2348 | @code |
| 2349 | UINT64 Msr; |
| 2350 | |
| 2351 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1); |
| 2352 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr); |
| 2353 | @endcode |
| 2354 | @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM. |
| 2355 | **/ |
| 2356 | #define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD |
| 2357 | |
| 2358 | /** |
| 2359 | 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section |
| 2360 | 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to |
| 2361 | 8-MByte L3 Cache.". |
| 2362 | |
| 2363 | @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE) |
| 2364 | @param EAX Lower 32-bits of MSR value. |
| 2365 | @param EDX Upper 32-bits of MSR value. |
| 2366 | |
| 2367 | <b>Example usage</b> |
| 2368 | @code |
| 2369 | UINT64 Msr; |
| 2370 | |
| 2371 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0); |
| 2372 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr); |
| 2373 | @endcode |
| 2374 | @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM. |
| 2375 | **/ |
| 2376 | #define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE |
| 2377 | |
| 2378 | /** |
| 2379 | 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W). |
| 2380 | |
| 2381 | @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF) |
| 2382 | @param EAX Lower 32-bits of MSR value. |
| 2383 | @param EDX Upper 32-bits of MSR value. |
| 2384 | |
| 2385 | <b>Example usage</b> |
| 2386 | @code |
| 2387 | UINT64 Msr; |
| 2388 | |
| 2389 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1); |
| 2390 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr); |
| 2391 | @endcode |
| 2392 | @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM. |
| 2393 | **/ |
| 2394 | #define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF |
| 2395 | |
| 2396 | /** |
| 2397 | 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section |
| 2398 | 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to |
| 2399 | 8-MByte L3 Cache.". |
| 2400 | |
| 2401 | @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0) |
| 2402 | @param EAX Lower 32-bits of MSR value. |
| 2403 | @param EDX Upper 32-bits of MSR value. |
| 2404 | |
| 2405 | <b>Example usage</b> |
| 2406 | @code |
| 2407 | UINT64 Msr; |
| 2408 | |
| 2409 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0); |
| 2410 | AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr); |
| 2411 | @endcode |
| 2412 | @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM. |
| 2413 | **/ |
| 2414 | #define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0 |
| 2415 | |
| 2416 | /** |
| 2417 | 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W). |
| 2418 | |
| 2419 | @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1) |
| 2420 | @param EAX Lower 32-bits of MSR value. |
| 2421 | @param EDX Upper 32-bits of MSR value. |
| 2422 | |
| 2423 | <b>Example usage</b> |
| 2424 | @code |
| 2425 | UINT64 Msr; |
| 2426 | |
| 2427 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1); |
| 2428 | AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr); |
| 2429 | @endcode |
| 2430 | @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM. |
| 2431 | **/ |
| 2432 | #define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1 |
| 2433 | |
| 2434 | /** |
| 2435 | 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6, |
| 2436 | "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte |
| 2437 | L3 Cache.". |
| 2438 | |
| 2439 | @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2) |
| 2440 | @param EAX Lower 32-bits of MSR value. |
| 2441 | @param EDX Upper 32-bits of MSR value. |
| 2442 | |
| 2443 | <b>Example usage</b> |
| 2444 | @code |
| 2445 | UINT64 Msr; |
| 2446 | |
| 2447 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6); |
| 2448 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr); |
| 2449 | @endcode |
| 2450 | @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM. |
| 2451 | **/ |
| 2452 | #define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2 |
| 2453 | |
| 2454 | /** |
| 2455 | 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6, |
| 2456 | "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte |
| 2457 | L3 Cache.". |
| 2458 | |
| 2459 | @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3) |
| 2460 | @param EAX Lower 32-bits of MSR value. |
| 2461 | @param EDX Upper 32-bits of MSR value. |
| 2462 | |
| 2463 | <b>Example usage</b> |
| 2464 | @code |
| 2465 | UINT64 Msr; |
| 2466 | |
| 2467 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7); |
| 2468 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr); |
| 2469 | @endcode |
| 2470 | @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM. |
| 2471 | **/ |
| 2472 | #define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3 |
| 2473 | |
| 2474 | /** |
| 2475 | 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section |
| 2476 | 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to |
| 2477 | 8MByte L3 Cache.". |
| 2478 | |
| 2479 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC) |
| 2480 | @param EAX Lower 32-bits of MSR value. |
| 2481 | @param EDX Upper 32-bits of MSR value. |
| 2482 | |
| 2483 | <b>Example usage</b> |
| 2484 | @code |
| 2485 | UINT64 Msr; |
| 2486 | |
| 2487 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0); |
| 2488 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr); |
| 2489 | @endcode |
| 2490 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM. |
| 2491 | **/ |
| 2492 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC |
| 2493 | |
| 2494 | /** |
| 2495 | 6. Shared. GBUSQ Event Control and Counter Register (R/W). |
| 2496 | |
| 2497 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD) |
| 2498 | @param EAX Lower 32-bits of MSR value. |
| 2499 | @param EDX Upper 32-bits of MSR value. |
| 2500 | |
| 2501 | <b>Example usage</b> |
| 2502 | @code |
| 2503 | UINT64 Msr; |
| 2504 | |
| 2505 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1); |
| 2506 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr); |
| 2507 | @endcode |
| 2508 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM. |
| 2509 | **/ |
| 2510 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD |
| 2511 | |
| 2512 | /** |
| 2513 | 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section |
| 2514 | 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to |
| 2515 | 8MByte L3 Cache.". |
| 2516 | |
| 2517 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE) |
| 2518 | @param EAX Lower 32-bits of MSR value. |
| 2519 | @param EDX Upper 32-bits of MSR value. |
| 2520 | |
| 2521 | <b>Example usage</b> |
| 2522 | @code |
| 2523 | UINT64 Msr; |
| 2524 | |
| 2525 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2); |
| 2526 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr); |
| 2527 | @endcode |
| 2528 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM. |
| 2529 | **/ |
| 2530 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE |
| 2531 | |
| 2532 | /** |
| 2533 | 6. Shared. GSNPQ Event Control and Counter Register (R/W). |
| 2534 | |
| 2535 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF) |
| 2536 | @param EAX Lower 32-bits of MSR value. |
| 2537 | @param EDX Upper 32-bits of MSR value. |
| 2538 | |
| 2539 | <b>Example usage</b> |
| 2540 | @code |
| 2541 | UINT64 Msr; |
| 2542 | |
| 2543 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3); |
| 2544 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr); |
| 2545 | @endcode |
| 2546 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM. |
| 2547 | **/ |
| 2548 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF |
| 2549 | |
| 2550 | /** |
| 2551 | 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6, |
| 2552 | "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte |
| 2553 | L3 Cache.". |
| 2554 | |
| 2555 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0) |
| 2556 | @param EAX Lower 32-bits of MSR value. |
| 2557 | @param EDX Upper 32-bits of MSR value. |
| 2558 | |
| 2559 | <b>Example usage</b> |
| 2560 | @code |
| 2561 | UINT64 Msr; |
| 2562 | |
| 2563 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4); |
| 2564 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr); |
| 2565 | @endcode |
| 2566 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM. |
| 2567 | **/ |
| 2568 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0 |
| 2569 | |
| 2570 | /** |
| 2571 | 6. Shared. FSB Event Control and Counter Register (R/W). |
| 2572 | |
| 2573 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1) |
| 2574 | @param EAX Lower 32-bits of MSR value. |
| 2575 | @param EDX Upper 32-bits of MSR value. |
| 2576 | |
| 2577 | <b>Example usage</b> |
| 2578 | @code |
| 2579 | UINT64 Msr; |
| 2580 | |
| 2581 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5); |
| 2582 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr); |
| 2583 | @endcode |
| 2584 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM. |
| 2585 | **/ |
| 2586 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1 |
| 2587 | |
| 2588 | /** |
| 2589 | 6. Shared. FSB Event Control and Counter Register (R/W). |
| 2590 | |
| 2591 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2) |
| 2592 | @param EAX Lower 32-bits of MSR value. |
| 2593 | @param EDX Upper 32-bits of MSR value. |
| 2594 | |
| 2595 | <b>Example usage</b> |
| 2596 | @code |
| 2597 | UINT64 Msr; |
| 2598 | |
| 2599 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6); |
| 2600 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr); |
| 2601 | @endcode |
| 2602 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM. |
| 2603 | **/ |
| 2604 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2 |
| 2605 | |
| 2606 | /** |
| 2607 | 6. Shared. FSB Event Control and Counter Register (R/W). |
| 2608 | |
| 2609 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3) |
| 2610 | @param EAX Lower 32-bits of MSR value. |
| 2611 | @param EDX Upper 32-bits of MSR value. |
| 2612 | |
| 2613 | <b>Example usage</b> |
| 2614 | @code |
| 2615 | UINT64 Msr; |
| 2616 | |
| 2617 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7); |
| 2618 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr); |
| 2619 | @endcode |
| 2620 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM. |
| 2621 | **/ |
| 2622 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3 |
| 2623 | |
| 2624 | #endif |