Ronak Kanabar | 1ae366f | 2023-06-07 01:21:56 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | MSR Definitions for Intel processors based on the Broadwell microarchitecture. |
| 3 | |
| 4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures |
| 5 | are provided for MSRs that contain one or more bit fields. If the MSR value |
| 6 | returned is a single 32-bit or 64-bit value, then a data structure is not |
| 7 | provided for that MSR. |
| 8 | |
| 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR> |
| 10 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 11 | |
| 12 | @par Specification Reference: |
| 13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, |
| 14 | May 2018, Volume 4: Model-Specific-Registers (MSR) |
| 15 | |
| 16 | **/ |
| 17 | |
| 18 | #ifndef __BROADWELL_MSR_H__ |
| 19 | #define __BROADWELL_MSR_H__ |
| 20 | |
| 21 | #include <Register/Intel/ArchitecturalMsr.h> |
| 22 | |
| 23 | /** |
| 24 | Is Intel processors based on the Broadwell microarchitecture? |
| 25 | |
| 26 | @param DisplayFamily Display Family ID |
| 27 | @param DisplayModel Display Model ID |
| 28 | |
| 29 | @retval TRUE Yes, it is. |
| 30 | @retval FALSE No, it isn't. |
| 31 | **/ |
| 32 | #define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \ |
| 33 | (DisplayFamily == 0x06 && \ |
| 34 | ( \ |
| 35 | DisplayModel == 0x3D || \ |
| 36 | DisplayModel == 0x47 || \ |
| 37 | DisplayModel == 0x4F || \ |
| 38 | DisplayModel == 0x56 \ |
| 39 | ) \ |
| 40 | ) |
| 41 | |
| 42 | /** |
| 43 | Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control |
| 44 | Facilities.". |
| 45 | |
| 46 | @param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E) |
| 47 | @param EAX Lower 32-bits of MSR value. |
| 48 | Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER. |
| 49 | @param EDX Upper 32-bits of MSR value. |
| 50 | Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER. |
| 51 | |
| 52 | <b>Example usage</b> |
| 53 | @code |
| 54 | MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; |
| 55 | |
| 56 | Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS); |
| 57 | AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64); |
| 58 | @endcode |
| 59 | @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. |
| 60 | **/ |
| 61 | #define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E |
| 62 | |
| 63 | /** |
| 64 | MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS |
| 65 | **/ |
| 66 | typedef union { |
| 67 | /// |
| 68 | /// Individual bit fields |
| 69 | /// |
| 70 | struct { |
| 71 | /// |
| 72 | /// [Bit 0] Ovf_PMC0. |
| 73 | /// |
| 74 | UINT32 Ovf_PMC0 : 1; |
| 75 | /// |
| 76 | /// [Bit 1] Ovf_PMC1. |
| 77 | /// |
| 78 | UINT32 Ovf_PMC1 : 1; |
| 79 | /// |
| 80 | /// [Bit 2] Ovf_PMC2. |
| 81 | /// |
| 82 | UINT32 Ovf_PMC2 : 1; |
| 83 | /// |
| 84 | /// [Bit 3] Ovf_PMC3. |
| 85 | /// |
| 86 | UINT32 Ovf_PMC3 : 1; |
| 87 | UINT32 Reserved1 : 28; |
| 88 | /// |
| 89 | /// [Bit 32] Ovf_FixedCtr0. |
| 90 | /// |
| 91 | UINT32 Ovf_FixedCtr0 : 1; |
| 92 | /// |
| 93 | /// [Bit 33] Ovf_FixedCtr1. |
| 94 | /// |
| 95 | UINT32 Ovf_FixedCtr1 : 1; |
| 96 | /// |
| 97 | /// [Bit 34] Ovf_FixedCtr2. |
| 98 | /// |
| 99 | UINT32 Ovf_FixedCtr2 : 1; |
| 100 | UINT32 Reserved2 : 20; |
| 101 | /// |
| 102 | /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical |
| 103 | /// Addresses (ToPA).". |
| 104 | /// |
| 105 | UINT32 Trace_ToPA_PMI : 1; |
| 106 | UINT32 Reserved3 : 5; |
| 107 | /// |
| 108 | /// [Bit 61] Ovf_Uncore. |
| 109 | /// |
| 110 | UINT32 Ovf_Uncore : 1; |
| 111 | /// |
| 112 | /// [Bit 62] Ovf_BufDSSAVE. |
| 113 | /// |
| 114 | UINT32 OvfBuf : 1; |
| 115 | /// |
| 116 | /// [Bit 63] CondChgd. |
| 117 | /// |
| 118 | UINT32 CondChgd : 1; |
| 119 | } Bits; |
| 120 | /// |
| 121 | /// All bit fields as a 64-bit value |
| 122 | /// |
| 123 | UINT64 Uint64; |
| 124 | } MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER; |
| 125 | |
| 126 | /** |
| 127 | Core. C-State Configuration Control (R/W) Note: C-state values are processor |
| 128 | specific C-state code names, unrelated to MWAIT extension C-state parameters |
| 129 | or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__. |
| 130 | |
| 131 | @param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2) |
| 132 | @param EAX Lower 32-bits of MSR value. |
| 133 | Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER. |
| 134 | @param EDX Upper 32-bits of MSR value. |
| 135 | Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER. |
| 136 | |
| 137 | <b>Example usage</b> |
| 138 | @code |
| 139 | MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr; |
| 140 | |
| 141 | Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL); |
| 142 | AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64); |
| 143 | @endcode |
| 144 | @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM. |
| 145 | **/ |
| 146 | #define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2 |
| 147 | |
| 148 | /** |
| 149 | MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL |
| 150 | **/ |
| 151 | typedef union { |
| 152 | /// |
| 153 | /// Individual bit fields |
| 154 | /// |
| 155 | struct { |
| 156 | /// |
| 157 | /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest |
| 158 | /// processor-specific C-state code name (consuming the least power) for |
| 159 | /// the package. The default is set as factory-configured package C-state |
| 160 | /// limit. The following C-state code name encodings are supported: 0000b: |
| 161 | /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 |
| 162 | /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10. |
| 163 | /// |
| 164 | UINT32 Limit : 4; |
| 165 | UINT32 Reserved1 : 6; |
| 166 | /// |
| 167 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W). |
| 168 | /// |
| 169 | UINT32 IO_MWAIT : 1; |
| 170 | UINT32 Reserved2 : 4; |
| 171 | /// |
| 172 | /// [Bit 15] CFG Lock (R/WO). |
| 173 | /// |
| 174 | UINT32 CFGLock : 1; |
| 175 | UINT32 Reserved3 : 9; |
| 176 | /// |
| 177 | /// [Bit 25] C3 State Auto Demotion Enable (R/W). |
| 178 | /// |
| 179 | UINT32 C3AutoDemotion : 1; |
| 180 | /// |
| 181 | /// [Bit 26] C1 State Auto Demotion Enable (R/W). |
| 182 | /// |
| 183 | UINT32 C1AutoDemotion : 1; |
| 184 | /// |
| 185 | /// [Bit 27] Enable C3 Undemotion (R/W). |
| 186 | /// |
| 187 | UINT32 C3Undemotion : 1; |
| 188 | /// |
| 189 | /// [Bit 28] Enable C1 Undemotion (R/W). |
| 190 | /// |
| 191 | UINT32 C1Undemotion : 1; |
| 192 | /// |
| 193 | /// [Bit 29] Enable Package C-State Auto-demotion (R/W). |
| 194 | /// |
| 195 | UINT32 CStateAutoDemotion : 1; |
| 196 | /// |
| 197 | /// [Bit 30] Enable Package C-State Undemotion (R/W). |
| 198 | /// |
| 199 | UINT32 CStateUndemotion : 1; |
| 200 | UINT32 Reserved4 : 1; |
| 201 | UINT32 Reserved5 : 32; |
| 202 | } Bits; |
| 203 | /// |
| 204 | /// All bit fields as a 32-bit value |
| 205 | /// |
| 206 | UINT32 Uint32; |
| 207 | /// |
| 208 | /// All bit fields as a 64-bit value |
| 209 | /// |
| 210 | UINT64 Uint64; |
| 211 | } MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER; |
| 212 | |
| 213 | /** |
| 214 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, |
| 215 | RW if MSR_PLATFORM_INFO.[28] = 1. |
| 216 | |
| 217 | @param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD) |
| 218 | @param EAX Lower 32-bits of MSR value. |
| 219 | Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER. |
| 220 | @param EDX Upper 32-bits of MSR value. |
| 221 | Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER. |
| 222 | |
| 223 | <b>Example usage</b> |
| 224 | @code |
| 225 | MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr; |
| 226 | |
| 227 | Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT); |
| 228 | @endcode |
| 229 | @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. |
| 230 | **/ |
| 231 | #define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD |
| 232 | |
| 233 | /** |
| 234 | MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT |
| 235 | **/ |
| 236 | typedef union { |
| 237 | /// |
| 238 | /// Individual bit fields |
| 239 | /// |
| 240 | struct { |
| 241 | /// |
| 242 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio |
| 243 | /// limit of 1 core active. |
| 244 | /// |
| 245 | UINT32 Maximum1C : 8; |
| 246 | /// |
| 247 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio |
| 248 | /// limit of 2 core active. |
| 249 | /// |
| 250 | UINT32 Maximum2C : 8; |
| 251 | /// |
| 252 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio |
| 253 | /// limit of 3 core active. |
| 254 | /// |
| 255 | UINT32 Maximum3C : 8; |
| 256 | /// |
| 257 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio |
| 258 | /// limit of 4 core active. |
| 259 | /// |
| 260 | UINT32 Maximum4C : 8; |
| 261 | /// |
| 262 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio |
| 263 | /// limit of 5core active. |
| 264 | /// |
| 265 | UINT32 Maximum5C : 8; |
| 266 | /// |
| 267 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio |
| 268 | /// limit of 6core active. |
| 269 | /// |
| 270 | UINT32 Maximum6C : 8; |
| 271 | UINT32 Reserved : 16; |
| 272 | } Bits; |
| 273 | /// |
| 274 | /// All bit fields as a 64-bit value |
| 275 | /// |
| 276 | UINT64 Uint64; |
| 277 | } MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER; |
| 278 | |
| 279 | /** |
| 280 | Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio |
| 281 | fields represent the widest possible range of uncore frequencies. Writing to |
| 282 | these fields allows software to control the minimum and the maximum |
| 283 | frequency that hardware will select. |
| 284 | |
| 285 | @param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620) |
| 286 | @param EAX Lower 32-bits of MSR value. |
| 287 | Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER. |
| 288 | @param EDX Upper 32-bits of MSR value. |
| 289 | Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER. |
| 290 | |
| 291 | <b>Example usage</b> |
| 292 | @code |
| 293 | MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr; |
| 294 | |
| 295 | Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT); |
| 296 | AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64); |
| 297 | @endcode |
| 298 | **/ |
| 299 | #define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620 |
| 300 | |
| 301 | /** |
| 302 | MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT |
| 303 | **/ |
| 304 | typedef union { |
| 305 | /// |
| 306 | /// Individual bit fields |
| 307 | /// |
| 308 | struct { |
| 309 | /// |
| 310 | /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the |
| 311 | /// LLC/Ring. |
| 312 | /// |
| 313 | UINT32 MAX_RATIO : 7; |
| 314 | UINT32 Reserved2 : 1; |
| 315 | /// |
| 316 | /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum |
| 317 | /// possible ratio of the LLC/Ring. |
| 318 | /// |
| 319 | UINT32 MIN_RATIO : 7; |
| 320 | UINT32 Reserved3 : 17; |
| 321 | UINT32 Reserved4 : 32; |
| 322 | } Bits; |
| 323 | /// |
| 324 | /// All bit fields as a 32-bit value |
| 325 | /// |
| 326 | UINT32 Uint32; |
| 327 | /// |
| 328 | /// All bit fields as a 64-bit value |
| 329 | /// |
| 330 | UINT64 Uint64; |
| 331 | } MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER; |
| 332 | |
| 333 | /** |
| 334 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL |
| 335 | Domains.". |
| 336 | |
| 337 | @param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639) |
| 338 | @param EAX Lower 32-bits of MSR value. |
| 339 | @param EDX Upper 32-bits of MSR value. |
| 340 | |
| 341 | <b>Example usage</b> |
| 342 | @code |
| 343 | UINT64 Msr; |
| 344 | |
| 345 | Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS); |
| 346 | @endcode |
| 347 | @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. |
| 348 | **/ |
| 349 | #define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639 |
| 350 | |
| 351 | #endif |