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review.coreboot.org / coreboot / 1ae366f071852ea3a3fd50aa23d1448ad57d0fb3 / . / src / vendorcode / intel / edk2 / edk2-stable202302 / MdePkg / Include / Protocol / DebugSupport.h
blob: 61808c27fe1d351b708bb2c07238d1bc74759c12 [file] [log] [blame]
Ronak Kanabar1ae366f2023-06-07 01:21:56 +0530[diff] [blame^]1/** @file
2 DebugSupport protocol and supporting definitions as defined in the UEFI2.4
3 specification.
4
5 The DebugSupport protocol is used by source level debuggers to abstract the
6 processor and handle context save and restore operations.
7
8Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
9Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
10Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
11
12SPDX-License-Identifier: BSD-2-Clause-Patent
13
14**/
15
16#ifndef __DEBUG_SUPPORT_H__
17#define __DEBUG_SUPPORT_H__
18
19#include <IndustryStandard/PeImage.h>
20
21typedef struct _EFI_DEBUG_SUPPORT_PROTOCOL EFI_DEBUG_SUPPORT_PROTOCOL;
22
23///
24/// Debug Support protocol {2755590C-6F3C-42FA-9EA4-A3BA543CDA25}.
25///
26#define EFI_DEBUG_SUPPORT_PROTOCOL_GUID \
27 { \
28 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \
29 }
30
31///
32/// Processor exception to be hooked.
33/// All exception types for IA32, X64, Itanium and EBC processors are defined.
34///
35typedef INTN EFI_EXCEPTION_TYPE;
36
37///
38/// IA-32 processor exception types.
39///
40#define EXCEPT_IA32_DIVIDE_ERROR 0
41#define EXCEPT_IA32_DEBUG 1
42#define EXCEPT_IA32_NMI 2
43#define EXCEPT_IA32_BREAKPOINT 3
44#define EXCEPT_IA32_OVERFLOW 4
45#define EXCEPT_IA32_BOUND 5
46#define EXCEPT_IA32_INVALID_OPCODE 6
47#define EXCEPT_IA32_DOUBLE_FAULT 8
48#define EXCEPT_IA32_INVALID_TSS 10
49#define EXCEPT_IA32_SEG_NOT_PRESENT 11
50#define EXCEPT_IA32_STACK_FAULT 12
51#define EXCEPT_IA32_GP_FAULT 13
52#define EXCEPT_IA32_PAGE_FAULT 14
53#define EXCEPT_IA32_FP_ERROR 16
54#define EXCEPT_IA32_ALIGNMENT_CHECK 17
55#define EXCEPT_IA32_MACHINE_CHECK 18
56#define EXCEPT_IA32_SIMD 19
57
58///
59/// FXSAVE_STATE.
60/// FP / MMX / XMM registers (see fxrstor instruction definition).
61///
62typedef struct {
63 UINT16 Fcw;
64 UINT16 Fsw;
65 UINT16 Ftw;
66 UINT16 Opcode;
67 UINT32 Eip;
68 UINT16 Cs;
69 UINT16 Reserved1;
70 UINT32 DataOffset;
71 UINT16 Ds;
72 UINT8 Reserved2[10];
73 UINT8 St0Mm0[10], Reserved3[6];
74 UINT8 St1Mm1[10], Reserved4[6];
75 UINT8 St2Mm2[10], Reserved5[6];
76 UINT8 St3Mm3[10], Reserved6[6];
77 UINT8 St4Mm4[10], Reserved7[6];
78 UINT8 St5Mm5[10], Reserved8[6];
79 UINT8 St6Mm6[10], Reserved9[6];
80 UINT8 St7Mm7[10], Reserved10[6];
81 UINT8 Xmm0[16];
82 UINT8 Xmm1[16];
83 UINT8 Xmm2[16];
84 UINT8 Xmm3[16];
85 UINT8 Xmm4[16];
86 UINT8 Xmm5[16];
87 UINT8 Xmm6[16];
88 UINT8 Xmm7[16];
89 UINT8 Reserved11[14 * 16];
90} EFI_FX_SAVE_STATE_IA32;
91
92///
93/// IA-32 processor context definition.
94///
95typedef struct {
96 UINT32 ExceptionData;
97 EFI_FX_SAVE_STATE_IA32 FxSaveState;
98 UINT32 Dr0;
99 UINT32 Dr1;
100 UINT32 Dr2;
101 UINT32 Dr3;
102 UINT32 Dr6;
103 UINT32 Dr7;
104 UINT32 Cr0;
105 UINT32 Cr1; /* Reserved */
106 UINT32 Cr2;
107 UINT32 Cr3;
108 UINT32 Cr4;
109 UINT32 Eflags;
110 UINT32 Ldtr;
111 UINT32 Tr;
112 UINT32 Gdtr[2];
113 UINT32 Idtr[2];
114 UINT32 Eip;
115 UINT32 Gs;
116 UINT32 Fs;
117 UINT32 Es;
118 UINT32 Ds;
119 UINT32 Cs;
120 UINT32 Ss;
121 UINT32 Edi;
122 UINT32 Esi;
123 UINT32 Ebp;
124 UINT32 Esp;
125 UINT32 Ebx;
126 UINT32 Edx;
127 UINT32 Ecx;
128 UINT32 Eax;
129} EFI_SYSTEM_CONTEXT_IA32;
130
131///
132/// x64 processor exception types.
133///
134#define EXCEPT_X64_DIVIDE_ERROR 0
135#define EXCEPT_X64_DEBUG 1
136#define EXCEPT_X64_NMI 2
137#define EXCEPT_X64_BREAKPOINT 3
138#define EXCEPT_X64_OVERFLOW 4
139#define EXCEPT_X64_BOUND 5
140#define EXCEPT_X64_INVALID_OPCODE 6
141#define EXCEPT_X64_DOUBLE_FAULT 8
142#define EXCEPT_X64_INVALID_TSS 10
143#define EXCEPT_X64_SEG_NOT_PRESENT 11
144#define EXCEPT_X64_STACK_FAULT 12
145#define EXCEPT_X64_GP_FAULT 13
146#define EXCEPT_X64_PAGE_FAULT 14
147#define EXCEPT_X64_FP_ERROR 16
148#define EXCEPT_X64_ALIGNMENT_CHECK 17
149#define EXCEPT_X64_MACHINE_CHECK 18
150#define EXCEPT_X64_SIMD 19
151
152///
153/// FXSAVE_STATE.
154/// FP / MMX / XMM registers (see fxrstor instruction definition).
155///
156typedef struct {
157 UINT16 Fcw;
158 UINT16 Fsw;
159 UINT16 Ftw;
160 UINT16 Opcode;
161 UINT64 Rip;
162 UINT64 DataOffset;
163 UINT8 Reserved1[8];
164 UINT8 St0Mm0[10], Reserved2[6];
165 UINT8 St1Mm1[10], Reserved3[6];
166 UINT8 St2Mm2[10], Reserved4[6];
167 UINT8 St3Mm3[10], Reserved5[6];
168 UINT8 St4Mm4[10], Reserved6[6];
169 UINT8 St5Mm5[10], Reserved7[6];
170 UINT8 St6Mm6[10], Reserved8[6];
171 UINT8 St7Mm7[10], Reserved9[6];
172 UINT8 Xmm0[16];
173 UINT8 Xmm1[16];
174 UINT8 Xmm2[16];
175 UINT8 Xmm3[16];
176 UINT8 Xmm4[16];
177 UINT8 Xmm5[16];
178 UINT8 Xmm6[16];
179 UINT8 Xmm7[16];
180 //
181 // NOTE: UEFI 2.0 spec definition as follows.
182 //
183 UINT8 Reserved11[14 * 16];
184} EFI_FX_SAVE_STATE_X64;
185
186///
187/// x64 processor context definition.
188///
189typedef struct {
190 UINT64 ExceptionData;
191 EFI_FX_SAVE_STATE_X64 FxSaveState;
192 UINT64 Dr0;
193 UINT64 Dr1;
194 UINT64 Dr2;
195 UINT64 Dr3;
196 UINT64 Dr6;
197 UINT64 Dr7;
198 UINT64 Cr0;
199 UINT64 Cr1; /* Reserved */
200 UINT64 Cr2;
201 UINT64 Cr3;
202 UINT64 Cr4;
203 UINT64 Cr8;
204 UINT64 Rflags;
205 UINT64 Ldtr;
206 UINT64 Tr;
207 UINT64 Gdtr[2];
208 UINT64 Idtr[2];
209 UINT64 Rip;
210 UINT64 Gs;
211 UINT64 Fs;
212 UINT64 Es;
213 UINT64 Ds;
214 UINT64 Cs;
215 UINT64 Ss;
216 UINT64 Rdi;
217 UINT64 Rsi;
218 UINT64 Rbp;
219 UINT64 Rsp;
220 UINT64 Rbx;
221 UINT64 Rdx;
222 UINT64 Rcx;
223 UINT64 Rax;
224 UINT64 R8;
225 UINT64 R9;
226 UINT64 R10;
227 UINT64 R11;
228 UINT64 R12;
229 UINT64 R13;
230 UINT64 R14;
231 UINT64 R15;
232} EFI_SYSTEM_CONTEXT_X64;
233
234///
235/// Itanium Processor Family Exception types.
236///
237#define EXCEPT_IPF_VHTP_TRANSLATION 0
238#define EXCEPT_IPF_INSTRUCTION_TLB 1
239#define EXCEPT_IPF_DATA_TLB 2
240#define EXCEPT_IPF_ALT_INSTRUCTION_TLB 3
241#define EXCEPT_IPF_ALT_DATA_TLB 4
242#define EXCEPT_IPF_DATA_NESTED_TLB 5
243#define EXCEPT_IPF_INSTRUCTION_KEY_MISSED 6
244#define EXCEPT_IPF_DATA_KEY_MISSED 7
245#define EXCEPT_IPF_DIRTY_BIT 8
246#define EXCEPT_IPF_INSTRUCTION_ACCESS_BIT 9
247#define EXCEPT_IPF_DATA_ACCESS_BIT 10
248#define EXCEPT_IPF_BREAKPOINT 11
249#define EXCEPT_IPF_EXTERNAL_INTERRUPT 12
250//
251// 13 - 19 reserved
252//
253#define EXCEPT_IPF_PAGE_NOT_PRESENT 20
254#define EXCEPT_IPF_KEY_PERMISSION 21
255#define EXCEPT_IPF_INSTRUCTION_ACCESS_RIGHTS 22
256#define EXCEPT_IPF_DATA_ACCESS_RIGHTS 23
257#define EXCEPT_IPF_GENERAL_EXCEPTION 24
258#define EXCEPT_IPF_DISABLED_FP_REGISTER 25
259#define EXCEPT_IPF_NAT_CONSUMPTION 26
260#define EXCEPT_IPF_SPECULATION 27
261//
262// 28 reserved
263//
264#define EXCEPT_IPF_DEBUG 29
265#define EXCEPT_IPF_UNALIGNED_REFERENCE 30
266#define EXCEPT_IPF_UNSUPPORTED_DATA_REFERENCE 31
267#define EXCEPT_IPF_FP_FAULT 32
268#define EXCEPT_IPF_FP_TRAP 33
269#define EXCEPT_IPF_LOWER_PRIVILEGE_TRANSFER_TRAP 34
270#define EXCEPT_IPF_TAKEN_BRANCH 35
271#define EXCEPT_IPF_SINGLE_STEP 36
272//
273// 37 - 44 reserved
274//
275#define EXCEPT_IPF_IA32_EXCEPTION 45
276#define EXCEPT_IPF_IA32_INTERCEPT 46
277#define EXCEPT_IPF_IA32_INTERRUPT 47
278
279///
280/// IPF processor context definition.
281///
282typedef struct {
283 //
284 // The first reserved field is necessary to preserve alignment for the correct
285 // bits in UNAT and to insure F2 is 16 byte aligned.
286 //
287 UINT64 Reserved;
288 UINT64 R1;
289 UINT64 R2;
290 UINT64 R3;
291 UINT64 R4;
292 UINT64 R5;
293 UINT64 R6;
294 UINT64 R7;
295 UINT64 R8;
296 UINT64 R9;
297 UINT64 R10;
298 UINT64 R11;
299 UINT64 R12;
300 UINT64 R13;
301 UINT64 R14;
302 UINT64 R15;
303 UINT64 R16;
304 UINT64 R17;
305 UINT64 R18;
306 UINT64 R19;
307 UINT64 R20;
308 UINT64 R21;
309 UINT64 R22;
310 UINT64 R23;
311 UINT64 R24;
312 UINT64 R25;
313 UINT64 R26;
314 UINT64 R27;
315 UINT64 R28;
316 UINT64 R29;
317 UINT64 R30;
318 UINT64 R31;
319
320 UINT64 F2[2];
321 UINT64 F3[2];
322 UINT64 F4[2];
323 UINT64 F5[2];
324 UINT64 F6[2];
325 UINT64 F7[2];
326 UINT64 F8[2];
327 UINT64 F9[2];
328 UINT64 F10[2];
329 UINT64 F11[2];
330 UINT64 F12[2];
331 UINT64 F13[2];
332 UINT64 F14[2];
333 UINT64 F15[2];
334 UINT64 F16[2];
335 UINT64 F17[2];
336 UINT64 F18[2];
337 UINT64 F19[2];
338 UINT64 F20[2];
339 UINT64 F21[2];
340 UINT64 F22[2];
341 UINT64 F23[2];
342 UINT64 F24[2];
343 UINT64 F25[2];
344 UINT64 F26[2];
345 UINT64 F27[2];
346 UINT64 F28[2];
347 UINT64 F29[2];
348 UINT64 F30[2];
349 UINT64 F31[2];
350
351 UINT64 Pr;
352
353 UINT64 B0;
354 UINT64 B1;
355 UINT64 B2;
356 UINT64 B3;
357 UINT64 B4;
358 UINT64 B5;
359 UINT64 B6;
360 UINT64 B7;
361
362 //
363 // application registers
364 //
365 UINT64 ArRsc;
366 UINT64 ArBsp;
367 UINT64 ArBspstore;
368 UINT64 ArRnat;
369
370 UINT64 ArFcr;
371
372 UINT64 ArEflag;
373 UINT64 ArCsd;
374 UINT64 ArSsd;
375 UINT64 ArCflg;
376 UINT64 ArFsr;
377 UINT64 ArFir;
378 UINT64 ArFdr;
379
380 UINT64 ArCcv;
381
382 UINT64 ArUnat;
383
384 UINT64 ArFpsr;
385
386 UINT64 ArPfs;
387 UINT64 ArLc;
388 UINT64 ArEc;
389
390 //
391 // control registers
392 //
393 UINT64 CrDcr;
394 UINT64 CrItm;
395 UINT64 CrIva;
396 UINT64 CrPta;
397 UINT64 CrIpsr;
398 UINT64 CrIsr;
399 UINT64 CrIip;
400 UINT64 CrIfa;
401 UINT64 CrItir;
402 UINT64 CrIipa;
403 UINT64 CrIfs;
404 UINT64 CrIim;
405 UINT64 CrIha;
406
407 //
408 // debug registers
409 //
410 UINT64 Dbr0;
411 UINT64 Dbr1;
412 UINT64 Dbr2;
413 UINT64 Dbr3;
414 UINT64 Dbr4;
415 UINT64 Dbr5;
416 UINT64 Dbr6;
417 UINT64 Dbr7;
418
419 UINT64 Ibr0;
420 UINT64 Ibr1;
421 UINT64 Ibr2;
422 UINT64 Ibr3;
423 UINT64 Ibr4;
424 UINT64 Ibr5;
425 UINT64 Ibr6;
426 UINT64 Ibr7;
427
428 //
429 // virtual registers - nat bits for R1-R31
430 //
431 UINT64 IntNat;
432} EFI_SYSTEM_CONTEXT_IPF;
433
434///
435/// EBC processor exception types.
436///
437#define EXCEPT_EBC_UNDEFINED 0
438#define EXCEPT_EBC_DIVIDE_ERROR 1
439#define EXCEPT_EBC_DEBUG 2
440#define EXCEPT_EBC_BREAKPOINT 3
441#define EXCEPT_EBC_OVERFLOW 4
442#define EXCEPT_EBC_INVALID_OPCODE 5 ///< Opcode out of range.
443#define EXCEPT_EBC_STACK_FAULT 6
444#define EXCEPT_EBC_ALIGNMENT_CHECK 7
445#define EXCEPT_EBC_INSTRUCTION_ENCODING 8 ///< Malformed instruction.
446#define EXCEPT_EBC_BAD_BREAK 9 ///< BREAK 0 or undefined BREAK.
447#define EXCEPT_EBC_STEP 10 ///< To support debug stepping.
448///
449/// For coding convenience, define the maximum valid EBC exception.
450///
451#define MAX_EBC_EXCEPTION EXCEPT_EBC_STEP
452
453///
454/// EBC processor context definition.
455///
456typedef struct {
457 UINT64 R0;
458 UINT64 R1;
459 UINT64 R2;
460 UINT64 R3;
461 UINT64 R4;
462 UINT64 R5;
463 UINT64 R6;
464 UINT64 R7;
465 UINT64 Flags;
466 UINT64 ControlFlags;
467 UINT64 Ip;
468} EFI_SYSTEM_CONTEXT_EBC;
469
470///
471/// ARM processor exception types.
472///
473#define EXCEPT_ARM_RESET 0
474#define EXCEPT_ARM_UNDEFINED_INSTRUCTION 1
475#define EXCEPT_ARM_SOFTWARE_INTERRUPT 2
476#define EXCEPT_ARM_PREFETCH_ABORT 3
477#define EXCEPT_ARM_DATA_ABORT 4
478#define EXCEPT_ARM_RESERVED 5
479#define EXCEPT_ARM_IRQ 6
480#define EXCEPT_ARM_FIQ 7
481
482///
483/// For coding convenience, define the maximum valid ARM exception.
484///
485#define MAX_ARM_EXCEPTION EXCEPT_ARM_FIQ
486
487///
488/// ARM processor context definition.
489///
490typedef struct {
491 UINT32 R0;
492 UINT32 R1;
493 UINT32 R2;
494 UINT32 R3;
495 UINT32 R4;
496 UINT32 R5;
497 UINT32 R6;
498 UINT32 R7;
499 UINT32 R8;
500 UINT32 R9;
501 UINT32 R10;
502 UINT32 R11;
503 UINT32 R12;
504 UINT32 SP;
505 UINT32 LR;
506 UINT32 PC;
507 UINT32 CPSR;
508 UINT32 DFSR;
509 UINT32 DFAR;
510 UINT32 IFSR;
511 UINT32 IFAR;
512} EFI_SYSTEM_CONTEXT_ARM;
513
514///
515/// AARCH64 processor exception types.
516///
517#define EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS 0
518#define EXCEPT_AARCH64_IRQ 1
519#define EXCEPT_AARCH64_FIQ 2
520#define EXCEPT_AARCH64_SERROR 3
521
522///
523/// For coding convenience, define the maximum valid ARM exception.
524///
525#define MAX_AARCH64_EXCEPTION EXCEPT_AARCH64_SERROR
526
527typedef struct {
528 // General Purpose Registers
529 UINT64 X0;
530 UINT64 X1;
531 UINT64 X2;
532 UINT64 X3;
533 UINT64 X4;
534 UINT64 X5;
535 UINT64 X6;
536 UINT64 X7;
537 UINT64 X8;
538 UINT64 X9;
539 UINT64 X10;
540 UINT64 X11;
541 UINT64 X12;
542 UINT64 X13;
543 UINT64 X14;
544 UINT64 X15;
545 UINT64 X16;
546 UINT64 X17;
547 UINT64 X18;
548 UINT64 X19;
549 UINT64 X20;
550 UINT64 X21;
551 UINT64 X22;
552 UINT64 X23;
553 UINT64 X24;
554 UINT64 X25;
555 UINT64 X26;
556 UINT64 X27;
557 UINT64 X28;
558 UINT64 FP; // x29 - Frame pointer
559 UINT64 LR; // x30 - Link Register
560 UINT64 SP; // x31 - Stack pointer
561
562 // FP/SIMD Registers
563 UINT64 V0[2];
564 UINT64 V1[2];
565 UINT64 V2[2];
566 UINT64 V3[2];
567 UINT64 V4[2];
568 UINT64 V5[2];
569 UINT64 V6[2];
570 UINT64 V7[2];
571 UINT64 V8[2];
572 UINT64 V9[2];
573 UINT64 V10[2];
574 UINT64 V11[2];
575 UINT64 V12[2];
576 UINT64 V13[2];
577 UINT64 V14[2];
578 UINT64 V15[2];
579 UINT64 V16[2];
580 UINT64 V17[2];
581 UINT64 V18[2];
582 UINT64 V19[2];
583 UINT64 V20[2];
584 UINT64 V21[2];
585 UINT64 V22[2];
586 UINT64 V23[2];
587 UINT64 V24[2];
588 UINT64 V25[2];
589 UINT64 V26[2];
590 UINT64 V27[2];
591 UINT64 V28[2];
592 UINT64 V29[2];
593 UINT64 V30[2];
594 UINT64 V31[2];
595
596 UINT64 ELR; // Exception Link Register
597 UINT64 SPSR; // Saved Processor Status Register
598 UINT64 FPSR; // Floating Point Status Register
599 UINT64 ESR; // Exception syndrome register
600 UINT64 FAR; // Fault Address Register
601} EFI_SYSTEM_CONTEXT_AARCH64;
602
603///
604/// RISC-V processor exception types.
605///
606#define EXCEPT_RISCV_INST_MISALIGNED 0
607#define EXCEPT_RISCV_INST_ACCESS_FAULT 1
608#define EXCEPT_RISCV_ILLEGAL_INST 2
609#define EXCEPT_RISCV_BREAKPOINT 3
610#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4
611#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5
612#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
613#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7
614#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8
615#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9
616#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10
617#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11
618
619#define EXCEPT_RISCV_SOFTWARE_INT 0x0
620#define EXCEPT_RISCV_TIMER_INT 0x1
621
622typedef struct {
623 UINT64 X0;
624 UINT64 X1;
625 UINT64 X2;
626 UINT64 X3;
627 UINT64 X4;
628 UINT64 X5;
629 UINT64 X6;
630 UINT64 X7;
631 UINT64 X8;
632 UINT64 X9;
633 UINT64 X10;
634 UINT64 X11;
635 UINT64 X12;
636 UINT64 X13;
637 UINT64 X14;
638 UINT64 X15;
639 UINT64 X16;
640 UINT64 X17;
641 UINT64 X18;
642 UINT64 X19;
643 UINT64 X20;
644 UINT64 X21;
645 UINT64 X22;
646 UINT64 X23;
647 UINT64 X24;
648 UINT64 X25;
649 UINT64 X26;
650 UINT64 X27;
651 UINT64 X28;
652 UINT64 X29;
653 UINT64 X30;
654 UINT64 X31;
655} EFI_SYSTEM_CONTEXT_RISCV64;
656
657//
658// LoongArch processor exception types.
659//
660#define EXCEPT_LOONGARCH_INT 0
661#define EXCEPT_LOONGARCH_PIL 1
662#define EXCEPT_LOONGARCH_PIS 2
663#define EXCEPT_LOONGARCH_PIF 3
664#define EXCEPT_LOONGARCH_PME 4
665#define EXCEPT_LOONGARCH_PNR 5
666#define EXCEPT_LOONGARCH_PNX 6
667#define EXCEPT_LOONGARCH_PPI 7
668#define EXCEPT_LOONGARCH_ADE 8
669#define EXCEPT_LOONGARCH_ALE 9
670#define EXCEPT_LOONGARCH_BCE 10
671#define EXCEPT_LOONGARCH_SYS 11
672#define EXCEPT_LOONGARCH_BRK 12
673#define EXCEPT_LOONGARCH_INE 13
674#define EXCEPT_LOONGARCH_IPE 14
675#define EXCEPT_LOONGARCH_FPD 15
676#define EXCEPT_LOONGARCH_SXD 16
677#define EXCEPT_LOONGARCH_ASXD 17
678#define EXCEPT_LOONGARCH_FPE 18
679#define EXCEPT_LOONGARCH_TBR 64 // For code only, there is no such type in the ISA spec, the TLB refill is defined for an independent exception.
680
681//
682// LoongArch processor Interrupt types.
683//
684#define EXCEPT_LOONGARCH_INT_SIP0 0
685#define EXCEPT_LOONGARCH_INT_SIP1 1
686#define EXCEPT_LOONGARCH_INT_IP0 2
687#define EXCEPT_LOONGARCH_INT_IP1 3
688#define EXCEPT_LOONGARCH_INT_IP2 4
689#define EXCEPT_LOONGARCH_INT_IP3 5
690#define EXCEPT_LOONGARCH_INT_IP4 6
691#define EXCEPT_LOONGARCH_INT_IP5 7
692#define EXCEPT_LOONGARCH_INT_IP6 8
693#define EXCEPT_LOONGARCH_INT_IP7 9
694#define EXCEPT_LOONGARCH_INT_PMC 10
695#define EXCEPT_LOONGARCH_INT_TIMER 11
696#define EXCEPT_LOONGARCH_INT_IPI 12
697
698//
699// For coding convenience, define the maximum valid
700// LoongArch interrupt.
701//
702#define MAX_LOONGARCH_INTERRUPT 14
703
704typedef struct {
705 UINT64 R0;
706 UINT64 R1;
707 UINT64 R2;
708 UINT64 R3;
709 UINT64 R4;
710 UINT64 R5;
711 UINT64 R6;
712 UINT64 R7;
713 UINT64 R8;
714 UINT64 R9;
715 UINT64 R10;
716 UINT64 R11;
717 UINT64 R12;
718 UINT64 R13;
719 UINT64 R14;
720 UINT64 R15;
721 UINT64 R16;
722 UINT64 R17;
723 UINT64 R18;
724 UINT64 R19;
725 UINT64 R20;
726 UINT64 R21;
727 UINT64 R22;
728 UINT64 R23;
729 UINT64 R24;
730 UINT64 R25;
731 UINT64 R26;
732 UINT64 R27;
733 UINT64 R28;
734 UINT64 R29;
735 UINT64 R30;
736 UINT64 R31;
737
738 UINT64 CRMD; // CuRrent MoDe information
739 UINT64 PRMD; // PRe-exception MoDe information
740 UINT64 EUEN; // Extended component Unit ENable
741 UINT64 MISC; // MISCellaneous controller
742 UINT64 ECFG; // Exception ConFiGuration
743 UINT64 ESTAT; // Exception STATus
744 UINT64 ERA; // Exception Return Address
745 UINT64 BADV; // BAD Virtual address
746 UINT64 BADI; // BAD Instruction
747} EFI_SYSTEM_CONTEXT_LOONGARCH64;
748
749///
750/// Universal EFI_SYSTEM_CONTEXT definition.
751///
752typedef union {
753 EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
754 EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
755 EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
756 EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
757 EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
758 EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
759 EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
760 EFI_SYSTEM_CONTEXT_LOONGARCH64 *SystemContextLoongArch64;
761} EFI_SYSTEM_CONTEXT;
762
763//
764// DebugSupport callback function prototypes
765//
766
767/**
768 Registers and enables an exception callback function for the specified exception.
769
770 @param ExceptionType Exception types in EBC, IA-32, x64, or IPF.
771 @param SystemContext Exception content.
772
773**/
774typedef
775VOID
776(EFIAPI *EFI_EXCEPTION_CALLBACK)(
777 IN EFI_EXCEPTION_TYPE ExceptionType,
778 IN OUT EFI_SYSTEM_CONTEXT SystemContext
779 );
780
781/**
782 Registers and enables the on-target debug agent's periodic entry point.
783
784 @param SystemContext Exception content.
785
786**/
787typedef
788VOID
789(EFIAPI *EFI_PERIODIC_CALLBACK)(
790 IN OUT EFI_SYSTEM_CONTEXT SystemContext
791 );
792
793///
794/// Machine type definition
795///
796typedef enum {
797 IsaIa32 = IMAGE_FILE_MACHINE_I386, ///< 0x014C
798 IsaX64 = IMAGE_FILE_MACHINE_X64, ///< 0x8664
799 IsaIpf = IMAGE_FILE_MACHINE_IA64, ///< 0x0200
800 IsaEbc = IMAGE_FILE_MACHINE_EBC, ///< 0x0EBC
801 IsaArm = IMAGE_FILE_MACHINE_ARMTHUMB_MIXED, ///< 0x01c2
802 IsaAArch64 = IMAGE_FILE_MACHINE_ARM64 ///< 0xAA64
803} EFI_INSTRUCTION_SET_ARCHITECTURE;
804
805//
806// DebugSupport member function definitions
807//
808
809/**
810 Returns the maximum value that may be used for the ProcessorIndex parameter in
811 RegisterPeriodicCallback() and RegisterExceptionCallback().
812
813 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
814 @param MaxProcessorIndex Pointer to a caller-allocated UINTN in which the maximum supported
815 processor index is returned.
816
817 @retval EFI_SUCCESS The function completed successfully.
818
819**/
820typedef
821EFI_STATUS
822(EFIAPI *EFI_GET_MAXIMUM_PROCESSOR_INDEX)(
823 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
824 OUT UINTN *MaxProcessorIndex
825 );
826
827/**
828 Registers a function to be called back periodically in interrupt context.
829
830 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
831 @param ProcessorIndex Specifies which processor the callback function applies to.
832 @param PeriodicCallback A pointer to a function of type PERIODIC_CALLBACK that is the main
833 periodic entry point of the debug agent.
834
835 @retval EFI_SUCCESS The function completed successfully.
836 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback
837 function was previously registered.
838 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback
839 function.
840
841**/
842typedef
843EFI_STATUS
844(EFIAPI *EFI_REGISTER_PERIODIC_CALLBACK)(
845 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
846 IN UINTN ProcessorIndex,
847 IN EFI_PERIODIC_CALLBACK PeriodicCallback
848 );
849
850/**
851 Registers a function to be called when a given processor exception occurs.
852
853 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
854 @param ProcessorIndex Specifies which processor the callback function applies to.
855 @param ExceptionCallback A pointer to a function of type EXCEPTION_CALLBACK that is called
856 when the processor exception specified by ExceptionType occurs.
857 @param ExceptionType Specifies which processor exception to hook.
858
859 @retval EFI_SUCCESS The function completed successfully.
860 @retval EFI_ALREADY_STARTED Non-NULL PeriodicCallback parameter when a callback
861 function was previously registered.
862 @retval EFI_OUT_OF_RESOURCES System has insufficient memory resources to register new callback
863 function.
864
865**/
866typedef
867EFI_STATUS
868(EFIAPI *EFI_REGISTER_EXCEPTION_CALLBACK)(
869 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
870 IN UINTN ProcessorIndex,
871 IN EFI_EXCEPTION_CALLBACK ExceptionCallback,
872 IN EFI_EXCEPTION_TYPE ExceptionType
873 );
874
875/**
876 Invalidates processor instruction cache for a memory range. Subsequent execution in this range
877 causes a fresh memory fetch to retrieve code to be executed.
878
879 @param This A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
880 @param ProcessorIndex Specifies which processor's instruction cache is to be invalidated.
881 @param Start Specifies the physical base of the memory range to be invalidated.
882 @param Length Specifies the minimum number of bytes in the processor's instruction
883 cache to invalidate.
884
885 @retval EFI_SUCCESS The function completed successfully.
886
887**/
888typedef
889EFI_STATUS
890(EFIAPI *EFI_INVALIDATE_INSTRUCTION_CACHE)(
891 IN EFI_DEBUG_SUPPORT_PROTOCOL *This,
892 IN UINTN ProcessorIndex,
893 IN VOID *Start,
894 IN UINT64 Length
895 );
896
897///
898/// This protocol provides the services to allow the debug agent to register
899/// callback functions that are called either periodically or when specific
900/// processor exceptions occur.
901///
902struct _EFI_DEBUG_SUPPORT_PROTOCOL {
903 ///
904 /// Declares the processor architecture for this instance of the EFI Debug Support protocol.
905 ///
906 EFI_INSTRUCTION_SET_ARCHITECTURE Isa;
907 EFI_GET_MAXIMUM_PROCESSOR_INDEX GetMaximumProcessorIndex;
908 EFI_REGISTER_PERIODIC_CALLBACK RegisterPeriodicCallback;
909 EFI_REGISTER_EXCEPTION_CALLBACK RegisterExceptionCallback;
910 EFI_INVALIDATE_INSTRUCTION_CACHE InvalidateInstructionCache;
911};
912
913extern EFI_GUID gEfiDebugSupportProtocolGuid;
914
915#endif