Ronak Kanabar | 1ae366f | 2023-06-07 01:21:56 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | Provides services to maintain instruction and data caches. |
| 3 | |
| 4 | The Cache Maintenance Library provides abstractions for basic processor cache operations. |
| 5 | It removes the need to use assembly in C code. |
| 6 | |
| 7 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> |
| 8 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 9 | |
| 10 | **/ |
| 11 | |
| 12 | #ifndef __CACHE_MAINTENANCE_LIB__ |
| 13 | #define __CACHE_MAINTENANCE_LIB__ |
| 14 | |
| 15 | /** |
| 16 | Invalidates the entire instruction cache in cache coherency domain of the |
| 17 | calling CPU. |
| 18 | |
| 19 | **/ |
| 20 | VOID |
| 21 | EFIAPI |
| 22 | InvalidateInstructionCache ( |
| 23 | VOID |
| 24 | ); |
| 25 | |
| 26 | /** |
| 27 | Invalidates a range of instruction cache lines in the cache coherency domain |
| 28 | of the calling CPU. |
| 29 | |
| 30 | Invalidates the instruction cache lines specified by Address and Length. If |
| 31 | Address is not aligned on a cache line boundary, then entire instruction |
| 32 | cache line containing Address is invalidated. If Address + Length is not |
| 33 | aligned on a cache line boundary, then the entire instruction cache line |
| 34 | containing Address + Length -1 is invalidated. This function may choose to |
| 35 | invalidate the entire instruction cache if that is more efficient than |
| 36 | invalidating the specified range. If Length is 0, then no instruction cache |
| 37 | lines are invalidated. Address is returned. |
| 38 | |
| 39 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). |
| 40 | |
| 41 | @param Address The base address of the instruction cache lines to |
| 42 | invalidate. If the CPU is in a physical addressing mode, then |
| 43 | Address is a physical address. If the CPU is in a virtual |
| 44 | addressing mode, then Address is a virtual address. |
| 45 | |
| 46 | @param Length The number of bytes to invalidate from the instruction cache. |
| 47 | |
| 48 | @return Address. |
| 49 | |
| 50 | **/ |
| 51 | VOID * |
| 52 | EFIAPI |
| 53 | InvalidateInstructionCacheRange ( |
| 54 | IN VOID *Address, |
| 55 | IN UINTN Length |
| 56 | ); |
| 57 | |
| 58 | /** |
| 59 | Writes Back and Invalidates the entire data cache in cache coherency domain |
| 60 | of the calling CPU. |
| 61 | |
| 62 | Writes Back and Invalidates the entire data cache in cache coherency domain |
| 63 | of the calling CPU. This function guarantees that all dirty cache lines are |
| 64 | written back to system memory, and also invalidates all the data cache lines |
| 65 | in the cache coherency domain of the calling CPU. |
| 66 | |
| 67 | **/ |
| 68 | VOID |
| 69 | EFIAPI |
| 70 | WriteBackInvalidateDataCache ( |
| 71 | VOID |
| 72 | ); |
| 73 | |
| 74 | /** |
| 75 | Writes Back and Invalidates a range of data cache lines in the cache |
| 76 | coherency domain of the calling CPU. |
| 77 | |
| 78 | Writes Back and Invalidate the data cache lines specified by Address and |
| 79 | Length. If Address is not aligned on a cache line boundary, then entire data |
| 80 | cache line containing Address is written back and invalidated. If Address + |
| 81 | Length is not aligned on a cache line boundary, then the entire data cache |
| 82 | line containing Address + Length -1 is written back and invalidated. This |
| 83 | function may choose to write back and invalidate the entire data cache if |
| 84 | that is more efficient than writing back and invalidating the specified |
| 85 | range. If Length is 0, then no data cache lines are written back and |
| 86 | invalidated. Address is returned. |
| 87 | |
| 88 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). |
| 89 | |
| 90 | @param Address The base address of the data cache lines to write back and |
| 91 | invalidate. If the CPU is in a physical addressing mode, then |
| 92 | Address is a physical address. If the CPU is in a virtual |
| 93 | addressing mode, then Address is a virtual address. |
| 94 | @param Length The number of bytes to write back and invalidate from the |
| 95 | data cache. |
| 96 | |
| 97 | @return Address of cache invalidation. |
| 98 | |
| 99 | **/ |
| 100 | VOID * |
| 101 | EFIAPI |
| 102 | WriteBackInvalidateDataCacheRange ( |
| 103 | IN VOID *Address, |
| 104 | IN UINTN Length |
| 105 | ); |
| 106 | |
| 107 | /** |
| 108 | Writes Back the entire data cache in cache coherency domain of the calling |
| 109 | CPU. |
| 110 | |
| 111 | Writes Back the entire data cache in cache coherency domain of the calling |
| 112 | CPU. This function guarantees that all dirty cache lines are written back to |
| 113 | system memory. This function may also invalidate all the data cache lines in |
| 114 | the cache coherency domain of the calling CPU. |
| 115 | |
| 116 | **/ |
| 117 | VOID |
| 118 | EFIAPI |
| 119 | WriteBackDataCache ( |
| 120 | VOID |
| 121 | ); |
| 122 | |
| 123 | /** |
| 124 | Writes Back a range of data cache lines in the cache coherency domain of the |
| 125 | calling CPU. |
| 126 | |
| 127 | Writes Back the data cache lines specified by Address and Length. If Address |
| 128 | is not aligned on a cache line boundary, then entire data cache line |
| 129 | containing Address is written back. If Address + Length is not aligned on a |
| 130 | cache line boundary, then the entire data cache line containing Address + |
| 131 | Length -1 is written back. This function may choose to write back the entire |
| 132 | data cache if that is more efficient than writing back the specified range. |
| 133 | If Length is 0, then no data cache lines are written back. This function may |
| 134 | also invalidate all the data cache lines in the specified range of the cache |
| 135 | coherency domain of the calling CPU. Address is returned. |
| 136 | |
| 137 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). |
| 138 | |
| 139 | @param Address The base address of the data cache lines to write back. If |
| 140 | the CPU is in a physical addressing mode, then Address is a |
| 141 | physical address. If the CPU is in a virtual addressing |
| 142 | mode, then Address is a virtual address. |
| 143 | @param Length The number of bytes to write back from the data cache. |
| 144 | |
| 145 | @return Address of cache written in main memory. |
| 146 | |
| 147 | **/ |
| 148 | VOID * |
| 149 | EFIAPI |
| 150 | WriteBackDataCacheRange ( |
| 151 | IN VOID *Address, |
| 152 | IN UINTN Length |
| 153 | ); |
| 154 | |
| 155 | /** |
| 156 | Invalidates the entire data cache in cache coherency domain of the calling |
| 157 | CPU. |
| 158 | |
| 159 | Invalidates the entire data cache in cache coherency domain of the calling |
| 160 | CPU. This function must be used with care because dirty cache lines are not |
| 161 | written back to system memory. It is typically used for cache diagnostics. If |
| 162 | the CPU does not support invalidation of the entire data cache, then a write |
| 163 | back and invalidate operation should be performed on the entire data cache. |
| 164 | |
| 165 | **/ |
| 166 | VOID |
| 167 | EFIAPI |
| 168 | InvalidateDataCache ( |
| 169 | VOID |
| 170 | ); |
| 171 | |
| 172 | /** |
| 173 | Invalidates a range of data cache lines in the cache coherency domain of the |
| 174 | calling CPU. |
| 175 | |
| 176 | Invalidates the data cache lines specified by Address and Length. If Address |
| 177 | is not aligned on a cache line boundary, then entire data cache line |
| 178 | containing Address is invalidated. If Address + Length is not aligned on a |
| 179 | cache line boundary, then the entire data cache line containing Address + |
| 180 | Length -1 is invalidated. This function must never invalidate any cache lines |
| 181 | outside the specified range. If Length is 0, the no data cache lines are |
| 182 | invalidated. Address is returned. This function must be used with care |
| 183 | because dirty cache lines are not written back to system memory. It is |
| 184 | typically used for cache diagnostics. If the CPU does not support |
| 185 | invalidation of a data cache range, then a write back and invalidate |
| 186 | operation should be performed on the data cache range. |
| 187 | |
| 188 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). |
| 189 | |
| 190 | @param Address The base address of the data cache lines to invalidate. If |
| 191 | the CPU is in a physical addressing mode, then Address is a |
| 192 | physical address. If the CPU is in a virtual addressing mode, |
| 193 | then Address is a virtual address. |
| 194 | @param Length The number of bytes to invalidate from the data cache. |
| 195 | |
| 196 | @return Address. |
| 197 | |
| 198 | **/ |
| 199 | VOID * |
| 200 | EFIAPI |
| 201 | InvalidateDataCacheRange ( |
| 202 | IN VOID *Address, |
| 203 | IN UINTN Length |
| 204 | ); |
| 205 | |
| 206 | #endif |