| Ronak Kanabar | 1ae366f | 2023-06-07 01:21:56 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | This file contains definitions for the SPD fields on an SDRAM. |
| 3 | |
| 4 | Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR> |
| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 6 | **/ |
| 7 | |
| 8 | #ifndef _SDRAM_SPD_H_ |
| 9 | #define _SDRAM_SPD_H_ |
| 10 | |
| 11 | #include <IndustryStandard/SdramSpdDdr3.h> |
| 12 | #include <IndustryStandard/SdramSpdDdr4.h> |
| 13 | #include <IndustryStandard/SdramSpdLpDdr.h> |
| 14 | |
| 15 | // |
| 16 | // SDRAM SPD field definitions |
| 17 | // |
| 18 | #define SPD_MEMORY_TYPE 2 |
| 19 | #define SPD_SDRAM_ROW_ADDR 3 |
| 20 | #define SPD_SDRAM_COL_ADDR 4 |
| 21 | #define SPD_SDRAM_MODULE_ROWS 5 |
| 22 | #define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6 |
| 23 | #define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7 |
| 24 | #define SPD_SDRAM_ECC_SUPPORT 11 |
| 25 | #define SPD_SDRAM_REFRESH 12 |
| 26 | #define SPD_SDRAM_WIDTH 13 |
| 27 | #define SPD_SDRAM_ERROR_WIDTH 14 |
| 28 | #define SPD_SDRAM_BURST_LENGTH 16 |
| 29 | #define SPD_SDRAM_NO_OF_BANKS 17 |
| 30 | #define SPD_SDRAM_CAS_LATENCY 18 |
| 31 | #define SPD_SDRAM_MODULE_ATTR 21 |
| 32 | |
| 33 | #define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency |
| 34 | #define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency |
| 35 | #define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency |
| 36 | #define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency |
| 37 | #define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency |
| 38 | #define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency |
| 39 | #define SPD_SDRAM_MIN_PRECHARGE 27 |
| 40 | #define SPD_SDRAM_ACTIVE_MIN 28 |
| 41 | #define SPD_SDRAM_RAS_CAS 29 |
| 42 | #define SPD_SDRAM_RAS_PULSE 30 |
| 43 | #define SPD_SDRAM_DENSITY 31 |
| 44 | |
| 45 | // |
| 46 | // Memory Type Definitions |
| 47 | // |
| 48 | #define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory |
| 49 | #define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory |
| 50 | #define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory |
| 51 | #define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory |
| 52 | #define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory |
| 53 | #define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory |
| 54 | #define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory |
| 55 | |
| 56 | // |
| 57 | // ECC Type Definitions |
| 58 | // |
| 59 | #define SPD_ECC_TYPE_NONE 0x00 ///< No error checking |
| 60 | #define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking |
| 61 | #define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only |
| 62 | // |
| 63 | // Module Attributes (Bit positions) |
| 64 | // |
| 65 | #define SPD_BUFFERED 0x01 |
| 66 | #define SPD_REGISTERED 0x02 |
| 67 | |
| 68 | #endif |