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review.coreboot.org / coreboot / 1ae366f071852ea3a3fd50aa23d1448ad57d0fb3 / . / src / vendorcode / intel / edk2 / edk2-stable202302 / MdePkg / Include / IndustryStandard / PciExpress50.h
blob: fcfa564c4cd4d4291021075e002e12433076d3a5 [file] [log] [blame]
Ronak Kanabar1ae366f2023-06-07 01:21:56 +0530[diff] [blame^]1/** @file
2Support for the PCI Express 5.0 standard.
3
4This header file may not define all structures. Please extend as required.
5
6Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>
7SPDX-License-Identifier: BSD-2-Clause-Patent
8
9**/
10
11#ifndef _PCIEXPRESS50_H_
12#define _PCIEXPRESS50_H_
13
14#include <IndustryStandard/PciExpress40.h>
15
16#pragma pack(1)
17
18/// The Physical Layer PCI Express Extended Capability definitions.
19///
20/// Based on section 7.7.6 of PCI Express Base Specification 5.0.
21///@{
22#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A
23#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1
24
25// Register offsets from Physical Layer PCI-E Ext Cap Header
26#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET 0x04
27#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET 0x08
28#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET 0x0C
29#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET 0x10
30#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET 0x14
31#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET 0x18
32#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET 0x1C
33#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x20
34
35typedef union {
36 struct {
37 UINT32 EqualizationByPassToHighestRateSupport : 1; // bit 0
38 UINT32 NoEqualizationNeededSupport : 1; // bit 1
39 UINT32 Reserved1 : 6; // Reserved bit 2:7
40 UINT32 ModifiedTSUsageMode0Support : 1; // bit 8
41 UINT32 ModifiedTSUsageMode1Support : 1; // bit 9
42 UINT32 ModifiedTSUsageMode2Support : 1; // bit 10
43 UINT32 ModifiedTSReservedUsageModes : 5; // bit 11:15
44 UINT32 Reserved2 : 16; // Reserved bit 16:31
45 } Bits;
46 UINT32 Uint32;
47} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;
48
49typedef union {
50 struct {
51 UINT32 EqualizationByPassToHighestRateDisable : 1; // bit 0
52 UINT32 NoEqualizationNeededDisable : 1; // bit 1
53 UINT32 Reserved1 : 6; // Reserved bit 2:7
54 UINT32 ModifiedTSUsageModeSelected : 3; // bit 8:10
55 UINT32 Reserved2 : 21; // Reserved bit 11:31
56 } Bits;
57 UINT32 Uint32;
58} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;
59
60typedef union {
61 struct {
62 UINT32 EqualizationComplete : 1; // bit 0
63 UINT32 EqualizationPhase1Success : 1; // bit 1
64 UINT32 EqualizationPhase2Success : 1; // bit 2
65 UINT32 EqualizationPhase3Success : 1; // bit 3
66 UINT32 LinkEqualizationRequest : 1; // bit 4
67 UINT32 ModifiedTSRcvd : 1; // bit 5
68 UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7
69 UINT32 TransmitterPrecodingOn : 1; // bit 8
70 UINT32 TransmitterPrecodeRequest : 1; // bit 9
71 UINT32 NoEqualizationNeededRcvd : 1; // bit 10
72 UINT32 Reserved : 21; // Reserved bit 11:31
73 } Bits;
74 UINT32 Uint32;
75} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;
76
77typedef union {
78 struct {
79 UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2
80 UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15
81 UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31
82 } Bits;
83 UINT32 Uint32;
84} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;
85
86typedef union {
87 struct {
88 UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23
89 UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
90 UINT32 Reserved : 6; // Reserved bit 26:31
91 } Bits;
92 UINT32 Uint32;
93} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;
94
95typedef union {
96 struct {
97 UINT32 TransModifiedTSUsageMode : 3; // bit 0:2
98 UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15
99 UINT32 TransModifiedTSVendorId : 16; // bit 16:31
100 } Bits;
101 UINT32 Uint32;
102} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;
103
104typedef union {
105 struct {
106 UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23
107 UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
108 UINT32 Reserved : 6; // Reserved bit 26:31
109 } Bits;
110 UINT32 Uint32;
111} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;
112
113typedef union {
114 struct {
115 UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
116 UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
117 } Bits;
118 UINT8 Uint8;
119} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;
120
121typedef struct {
122 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
123 PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablities;
124 PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control;
125 PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status;
126 PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModifiedTs1Data;
127 PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModifiedTs2Data;
128 PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransModifiedTs1Data;
129 PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransModifiedTs2Data;
130 PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
131} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;
132///@}
133
134#pragma pack()
135
136#endif