Ronak Kanabar | 1ae366f | 2023-06-07 01:21:56 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | The file lists the PCI class codes only defined in PCI code and ID assignment specification |
| 3 | revision 1.3. |
| 4 | |
| 5 | Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR> |
| 6 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 7 | |
| 8 | **/ |
| 9 | |
| 10 | #ifndef __PCI_CODE_ID_H__ |
| 11 | #define __PCI_CODE_ID_H__ |
| 12 | |
| 13 | /// |
| 14 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h. |
| 15 | /// |
| 16 | ///@{ |
| 17 | #define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00 |
| 18 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11 |
| 19 | #define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12 |
| 20 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13 |
| 21 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21 |
| 22 | #define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02 |
| 23 | #define PCI_CLASS_MASS_STORAGE_SAS 0x07 |
| 24 | #define PCI_IF_MASS_STORAGE_SAS 0x00 |
| 25 | #define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01 |
| 26 | #define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08 |
| 27 | #define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00 |
| 28 | #define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01 |
| 29 | #define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02 |
| 30 | ///@} |
| 31 | |
| 32 | /// |
| 33 | /// PCI_CLASS_NETWORK, Base Class 02h. |
| 34 | /// |
| 35 | ///@{ |
| 36 | #define PCI_CLASS_NETWORK_INFINIBAND 0x07 |
| 37 | ///@} |
| 38 | |
| 39 | /// |
| 40 | /// PCI_CLASS_MEDIA, Base Class 04h. |
| 41 | /// |
| 42 | ///@{ |
| 43 | #define PCI_CLASS_MEDIA_MIXED_MODE 0x03 |
| 44 | ///@} |
| 45 | |
| 46 | /// |
| 47 | /// PCI_CLASS_BRIDGE, Base Class 06h. |
| 48 | /// |
| 49 | ///@{ |
| 50 | #define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B |
| 51 | #define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00 |
| 52 | #define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01 |
| 53 | ///@} |
| 54 | |
| 55 | /// |
| 56 | /// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h. |
| 57 | /// |
| 58 | ///@{ |
| 59 | #define PCI_IF_HPET 0x03 |
| 60 | #define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05 |
| 61 | #define PCI_SUBCLASS_IOMMU 0x06 |
| 62 | ///@} |
| 63 | |
| 64 | /// |
| 65 | /// PCI_CLASS_PROCESSOR, Base Class 0Bh. |
| 66 | /// |
| 67 | ///@{ |
| 68 | #define PCI_SUBCLASS_PROC_OTHER 0x80 |
| 69 | ///@} |
| 70 | |
| 71 | /// |
| 72 | /// PCI_CLASS_SERIAL, Base Class 0Ch. |
| 73 | /// |
| 74 | ///@{ |
| 75 | #define PCI_IF_XHCI 0x30 |
| 76 | #define PCI_CLASS_SERIAL_OTHER 0x80 |
| 77 | ///@} |
| 78 | |
| 79 | /// |
| 80 | /// PCI_CLASS_SATELLITE, Base Class 0Fh. |
| 81 | /// |
| 82 | ///@{ |
| 83 | #define PCI_SUBCLASS_SATELLITE_OTHER 0x80 |
| 84 | ///@} |
| 85 | |
| 86 | /// |
| 87 | /// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h. |
| 88 | /// |
| 89 | ///@{ |
| 90 | #define PCI_CLASS_PROCESSING_ACCELERATOR 0x12 |
| 91 | ///@} |
| 92 | |
| 93 | #endif |