Ronak Kanabar | 1ae366f | 2023-06-07 01:21:56 +0530 | [diff] [blame^] | 1 | /** @file |
| 2 | Support for PCI 2.3 standard. |
| 3 | |
| 4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR> |
| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent |
| 6 | |
| 7 | **/ |
| 8 | |
| 9 | #ifndef _PCI23_H_ |
| 10 | #define _PCI23_H_ |
| 11 | |
| 12 | #include <IndustryStandard/Pci22.h> |
| 13 | |
| 14 | /// |
| 15 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h. |
| 16 | /// |
| 17 | ///@{ |
| 18 | #define PCI_CLASS_MASS_STORAGE_ATA 0x05 |
| 19 | #define PCI_IF_MASS_STORAGE_SINGLE_DMA 0x20 |
| 20 | #define PCI_IF_MASS_STORAGE_CHAINED_DMA 0x30 |
| 21 | ///@} |
| 22 | |
| 23 | /// |
| 24 | /// PCI_CLASS_NETWORK, Base Class 02h. |
| 25 | /// |
| 26 | ///@{ |
| 27 | #define PCI_CLASS_NETWORK_WORLDFIP 0x05 |
| 28 | #define PCI_CLASS_NETWORK_PICMG_MULTI_COMPUTING 0x06 |
| 29 | ///@} |
| 30 | |
| 31 | /// |
| 32 | /// PCI_CLASS_BRIDGE, Base Class 06h. |
| 33 | /// |
| 34 | ///@{ |
| 35 | #define PCI_CLASS_BRIDGE_SEMI_TRANSPARENT_P2P 0x09 |
| 36 | #define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_PRIMARY 0x40 |
| 37 | #define PCI_IF_BRIDGE_SEMI_TRANSPARENT_P2P_SECONDARY 0x80 |
| 38 | #define PCI_CLASS_BRIDGE_INFINIBAND_TO_PCI 0x0A |
| 39 | ///@} |
| 40 | |
| 41 | /// |
| 42 | /// PCI_CLASS_SCC, Base Class 07h. |
| 43 | /// |
| 44 | ///@{ |
| 45 | #define PCI_SUBCLASS_GPIB 0x04 |
| 46 | #define PCI_SUBCLASS_SMART_CARD 0x05 |
| 47 | ///@} |
| 48 | |
| 49 | /// |
| 50 | /// PCI_CLASS_SERIAL, Base Class 0Ch. |
| 51 | /// |
| 52 | ///@{ |
| 53 | #define PCI_IF_EHCI 0x20 |
| 54 | #define PCI_CLASS_SERIAL_IB 0x06 |
| 55 | #define PCI_CLASS_SERIAL_IPMI 0x07 |
| 56 | #define PCI_IF_IPMI_SMIC 0x00 |
| 57 | #define PCI_IF_IPMI_KCS 0x01 ///< Keyboard Controller Style |
| 58 | #define PCI_IF_IPMI_BT 0x02 ///< Block Transfer |
| 59 | #define PCI_CLASS_SERIAL_SERCOS 0x08 |
| 60 | #define PCI_CLASS_SERIAL_CANBUS 0x09 |
| 61 | ///@} |
| 62 | |
| 63 | /// |
| 64 | /// PCI_CLASS_WIRELESS, Base Class 0Dh. |
| 65 | /// |
| 66 | ///@{ |
| 67 | #define PCI_SUBCLASS_BLUETOOTH 0x11 |
| 68 | #define PCI_SUBCLASS_BROADBAND 0x12 |
| 69 | ///@} |
| 70 | |
| 71 | /// |
| 72 | /// PCI_CLASS_DPIO, Base Class 11h. |
| 73 | /// |
| 74 | ///@{ |
| 75 | #define PCI_SUBCLASS_PERFORMANCE_COUNTERS 0x01 |
| 76 | #define PCI_SUBCLASS_COMMUNICATION_SYNCHRONIZATION 0x10 |
| 77 | #define PCI_SUBCLASS_MANAGEMENT_CARD 0x20 |
| 78 | ///@} |
| 79 | |
| 80 | /// |
| 81 | /// defined in PCI Express Spec. |
| 82 | /// |
| 83 | #define PCI_EXP_MAX_CONFIG_OFFSET 0x1000 |
| 84 | |
| 85 | /// |
| 86 | /// PCI Capability List IDs and records. |
| 87 | /// |
| 88 | #define EFI_PCI_CAPABILITY_ID_PCIX 0x07 |
| 89 | #define EFI_PCI_CAPABILITY_ID_VENDOR 0x09 |
| 90 | |
| 91 | #pragma pack(1) |
| 92 | /// |
| 93 | /// PCI-X Capabilities List, |
| 94 | /// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b. |
| 95 | /// |
| 96 | typedef struct { |
| 97 | EFI_PCI_CAPABILITY_HDR Hdr; |
| 98 | UINT16 CommandReg; |
| 99 | UINT32 StatusReg; |
| 100 | } EFI_PCI_CAPABILITY_PCIX; |
| 101 | |
| 102 | /// |
| 103 | /// PCI-X Bridge Capabilities List, |
| 104 | /// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b. |
| 105 | /// |
| 106 | typedef struct { |
| 107 | EFI_PCI_CAPABILITY_HDR Hdr; |
| 108 | UINT16 SecStatusReg; |
| 109 | UINT32 StatusReg; |
| 110 | UINT32 SplitTransCtrlRegUp; |
| 111 | UINT32 SplitTransCtrlRegDn; |
| 112 | } EFI_PCI_CAPABILITY_PCIX_BRDG; |
| 113 | |
| 114 | /// |
| 115 | /// Vendor Specific Capability Header |
| 116 | /// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3 |
| 117 | /// |
| 118 | typedef struct { |
| 119 | EFI_PCI_CAPABILITY_HDR Hdr; |
| 120 | UINT8 Length; |
| 121 | } EFI_PCI_CAPABILITY_VENDOR_HDR; |
| 122 | |
| 123 | #pragma pack() |
| 124 | |
| 125 | #define PCI_CODE_TYPE_EFI_IMAGE 0x03 |
| 126 | |
| 127 | #endif |