blob: 0aad672fab66f65f6b75bf5f8e10a3239258b127 [file] [log] [blame]
Arthur Heymans7b9c1392017-04-09 20:40:39 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <console/console.h>
18#include <device/device.h>
19#include <device/pci.h>
20#include <device/pci_ids.h>
Arthur Heymans349e0852017-04-09 20:48:37 +020021#include "i82801jx.h"
Arthur Heymans7b9c1392017-04-09 20:40:39 +020022#include <device/pci_ehci.h>
23
24static void usb_ehci_init(struct device *dev)
25{
26 u32 reg32;
27
28 printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
29 reg32 = pci_read_config32(dev, PCI_COMMAND);
30 reg32 |= PCI_COMMAND_MASTER;
31 pci_write_config32(dev, PCI_COMMAND, reg32);
32
33 printk(BIOS_DEBUG, "done.\n");
34}
35
Elyes HAOUAS1a8c1df2018-05-13 13:36:44 +020036static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
37 unsigned device)
Arthur Heymans7b9c1392017-04-09 20:40:39 +020038{
39 u8 access_cntl;
40
41 access_cntl = pci_read_config8(dev, 0x80);
42
43 /* Enable writes to protected registers. */
44 pci_write_config8(dev, 0x80, access_cntl | 1);
45
46 if (!vendor || !device) {
47 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
48 pci_read_config32(dev, PCI_VENDOR_ID));
49 } else {
50 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
51 ((device & 0xffff) << 16) | (vendor & 0xffff));
52 }
53
54 /* Restore protection. */
55 pci_write_config8(dev, 0x80, access_cntl);
56}
57
58static const unsigned short pci_device_ids[] = {
Arthur Heymans349e0852017-04-09 20:48:37 +020059 0x3a3a,
60 0x3a6a,
61 0x3a3c,
62 0x3a6c,
Arthur Heymans7b9c1392017-04-09 20:40:39 +020063 0
64};
65
66static struct pci_operations lops_pci = {
67 .set_subsystem = &usb_ehci_set_subsystem,
68};
69
70static struct device_operations usb_ehci_ops = {
71 .read_resources = pci_ehci_read_resources,
72 .set_resources = pci_dev_set_resources,
73 .enable_resources = pci_dev_enable_resources,
74 .init = usb_ehci_init,
75 .scan_bus = 0,
76 .ops_pci = &lops_pci,
77};
78
79static const struct pci_driver pch_usb_ehci1 __pci_driver = {
80 .ops = &usb_ehci_ops,
81 .vendor = PCI_VENDOR_ID_INTEL,
82 .devices = pci_device_ids,
83};