Jamie Ryu | 0e7a52a | 2022-07-22 10:13:45 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <acpi/acpi.h> |
Jamie Ryu | 071d7f3 | 2022-07-22 12:29:57 -0700 | [diff] [blame] | 4 | #include <baseboard/ec.h> |
Jamie Ryu | 0e7a52a | 2022-07-22 10:13:45 -0700 | [diff] [blame] | 5 | |
| 6 | DefinitionBlock( |
| 7 | "dsdt.aml", |
| 8 | "DSDT", |
| 9 | ACPI_DSDT_REV_2, |
| 10 | OEM_ID, |
| 11 | ACPI_TABLE_CREATOR, |
| 12 | 0x20110725 |
| 13 | ) |
| 14 | { |
Jamie Ryu | 4d23b9f | 2022-07-22 12:03:53 -0700 | [diff] [blame] | 15 | #include <acpi/dsdt_top.asl> |
| 16 | #include <cpu/intel/common/acpi/cpu.asl> |
| 17 | #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> |
| 18 | #include <soc/intel/common/block/acpi/acpi/platform.asl> |
| 19 | |
| 20 | Scope (\_SB) { |
| 21 | Device (PCI0) |
| 22 | { |
| 23 | #include <soc/intel/common/block/acpi/acpi/northbridge.asl> |
| 24 | #include <soc/intel/meteorlake/acpi/southbridge.asl> |
Harsha B R | 1a832d0 | 2023-02-04 18:27:39 +0530 | [diff] [blame^] | 25 | #include <soc/intel/meteorlake/acpi/tcss.asl> |
Jamie Ryu | 4d23b9f | 2022-07-22 12:03:53 -0700 | [diff] [blame] | 26 | } |
| 27 | } |
| 28 | |
Jamie Ryu | 071d7f3 | 2022-07-22 12:29:57 -0700 | [diff] [blame] | 29 | |
| 30 | #if CONFIG(EC_GOOGLE_CHROMEEC) |
| 31 | /* Chrome OS Embedded Controller */ |
| 32 | Scope (\_SB.PCI0.LPCB) |
| 33 | { |
| 34 | /* ACPI code for EC SuperIO functions */ |
| 35 | #include <ec/google/chromeec/acpi/superio.asl> |
| 36 | /* ACPI code for EC functions */ |
| 37 | #include <ec/google/chromeec/acpi/ec.asl> |
| 38 | } |
| 39 | #endif |
| 40 | |
Jamie Ryu | 4d23b9f | 2022-07-22 12:03:53 -0700 | [diff] [blame] | 41 | #include <southbridge/intel/common/acpi/sleepstates.asl> |
Jamie Ryu | 0e7a52a | 2022-07-22 10:13:45 -0700 | [diff] [blame] | 42 | } |