blob: 1d9363c0066605393f523caaa69746ace3ae6e04 [file] [log] [blame]
Siyuan Wang3e32cc02013-07-09 17:16:20 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <device/pci_def.h>
21#include <device/device.h>
22
23/* warning: Porting.h includes an open #pragma pack(1) */
24#include "Porting.h"
25#include "AGESA.h"
26#include "amdlib.h"
27#include "dimmSpd.h"
28#include "chip.h"
29
30
31#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
32
33/*-----------------------------------------------------------------------------
34 *
35 * readSmbusByteData - read a single SPD byte from any offset
36 */
37
38static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
39{
40 unsigned int status;
41 UINT64 limit;
42
43 address |= 1; // set read bit
44
45 __outbyte (iobase + 0, 0xFF); // clear error status
46 __outbyte (iobase + 1, 0x1F); // clear error status
47 __outbyte (iobase + 3, offset); // offset in eeprom
48 __outbyte (iobase + 4, address); // slave address and read bit
49 __outbyte (iobase + 2, 0x48); // read byte command
50
51 // time limit to avoid hanging for unexpected error status (should never happen)
52 limit = __rdtsc () + 2000000000 / 10;
53 for (;;)
54 {
55 status = __inbyte (iobase);
56 if (__rdtsc () > limit) break;
57 if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
58 if ((status & 1) == 1) continue; // HostBusy set, keep waiting
59 break;
60 }
61
62 buffer [0] = __inbyte (iobase + 5);
63 if (status == 2) status = 0; // check for done with no errors
64 return status;
65}
66
67/*-----------------------------------------------------------------------------
68 *
69 * readSmbusByte - read a single SPD byte from the default offset
70 * this function is faster function readSmbusByteData
71 */
72
73static int readSmbusByte (int iobase, int address, char *buffer)
74{
75 unsigned int status;
76 UINT64 limit;
77
78 __outbyte (iobase + 0, 0xFF); // clear error status
79 __outbyte (iobase + 2, 0x44); // read command
80
81 // time limit to avoid hanging for unexpected error status
82 limit = __rdtsc () + 2000000000 / 10;
83 for (;;)
84 {
85 status = __inbyte (iobase);
86 if (__rdtsc () > limit) break;
87 if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
88 if ((status & 1) == 1) continue; // HostBusy set, keep waiting
89 break;
90 }
91
92 buffer [0] = __inbyte (iobase + 5);
93 if (status == 2) status = 0; // check for done with no errors
94 return status;
95}
96
97/*---------------------------------------------------------------------------
98 *
99 * readspd - Read one or more SPD bytes from a DIMM.
100 * Start with offset zero and read sequentially.
101 * Optimization relies on autoincrement to avoid
102 * sending offset for every byte.
103 * Reads 128 bytes in 7-8 ms at 400 KHz.
104 */
105
106static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
107{
108 int index, error;
109
110 /* read the first byte using offset zero */
111 error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
112 if (error) return error;
113
114 /* read the remaining bytes using auto-increment for speed */
115 for (index = 1; index < count; index++)
116 {
117 error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
118 if (error) return error;
119 }
120
121 return 0;
122}
123
124static void writePmReg (int reg, int data)
125{
126 __outbyte (0xCD6, reg);
127 __outbyte (0xCD7, data);
128}
129
130static void setupFch (int ioBase)
131{
132 writePmReg (0x2D, ioBase >> 8);
133 writePmReg (0x2C, ioBase | 1);
134 __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
135}
136
137AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
138{
139 int spdAddress, ioBase;
140 ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
141 ROMSTAGE_CONST struct northbridge_amd_agesa_family16kb_config *config = dev->chip_info;
142
143 if ((dev == 0) || (config == 0))
144 return AGESA_ERROR;
145
146 if (info->SocketId >= DIMENSION(config->spdAddrLookup ))
147 return AGESA_ERROR;
148 if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] ))
149 return AGESA_ERROR;
150 if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0]))
151 return AGESA_ERROR;
152
153 spdAddress = config->spdAddrLookup
154 [info->SocketId] [info->MemChannelId] [info->DimmId];
155
156 if (spdAddress == 0) return AGESA_ERROR;
157 ioBase = 0xB00;
158 setupFch (ioBase);
159 return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
160}