Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 2 | |
| 3 | #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H |
| 4 | #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H |
Aaron Durbin | e991945 | 2016-07-13 23:24:55 -0500 | [diff] [blame] | 5 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 6 | /* |
| 7 | * It does not matter where we put the SMBus I/O base, as long as we |
| 8 | * keep it consistent and don't interfere with other devices. Stage2 |
| 9 | * will relocate this anyways. |
| 10 | * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE |
| 11 | * again. But handling static BARs is a generic problem that should be |
| 12 | * solved in the device allocator. |
| 13 | */ |
| 14 | #define SMBUS_IO_BASE 0x0400 |
| 15 | /* TODO Make sure these don't get changed by stage2 */ |
| 16 | #define DEFAULT_GPIOBASE 0x0480 |
| 17 | #define DEFAULT_PMBASE 0x0500 |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 18 | |
Arthur Heymans | 2e464cf | 2018-06-13 00:07:09 +0200 | [diff] [blame] | 19 | #include <southbridge/intel/common/rcba.h> |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 20 | |
| 21 | #ifndef __ACPI__ |
| 22 | #define DEBUG_PERIODIC_SMIS 0 |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 23 | |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 24 | #include <device/device.h> |
Elyes HAOUAS | 9966703 | 2018-05-13 12:47:28 +0200 | [diff] [blame] | 25 | void i82801gx_enable(struct device *dev); |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 26 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 27 | void i82801gx_lpc_setup(void); |
Arthur Heymans | b236352 | 2019-11-11 18:40:50 +0100 | [diff] [blame] | 28 | void i82801gx_setup_bars(void); |
Arthur Heymans | 399b6c1 | 2019-11-11 19:12:57 +0100 | [diff] [blame] | 29 | void i82801gx_early_init(void); |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 30 | |
Arthur Heymans | 2437fe9 | 2019-10-04 13:59:29 +0200 | [diff] [blame] | 31 | void ich7_setup_cir(void); |
Uwe Hermann | 4028ce7 | 2010-12-07 19:16:07 +0000 | [diff] [blame] | 32 | |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 33 | #define MAINBOARD_POWER_OFF 0 |
| 34 | #define MAINBOARD_POWER_ON 1 |
| 35 | #define MAINBOARD_POWER_KEEP 2 |
| 36 | |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 37 | /* PCI Configuration Space (D30:F0): PCI2PCI */ |
| 38 | #define PSTS 0x06 |
| 39 | #define SMLT 0x1b |
| 40 | #define SECSTS 0x1e |
| 41 | #define INTR 0x3c |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 42 | |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 43 | #define ICH_PCIE_DEV_SLOT 28 |
| 44 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 45 | /* PCI Configuration Space (D31:F0): LPC */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 46 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 47 | #define SERIRQ_CNTL 0x64 |
Uwe Hermann | 65ebc79 | 2008-11-06 22:24:05 +0000 | [diff] [blame] | 48 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 49 | #define GEN_PMCON_1 0xa0 |
| 50 | #define GEN_PMCON_2 0xa2 |
| 51 | #define GEN_PMCON_3 0xa4 |
| 52 | |
Kyösti Mälkki | b85a87b | 2014-12-29 11:32:27 +0200 | [diff] [blame] | 53 | #define GPIO_ROUT 0xb8 |
| 54 | #define GPI_DISABLE 0x00 |
| 55 | #define GPI_IS_SMI 0x01 |
| 56 | #define GPI_IS_SCI 0x02 |
| 57 | #define GPI_IS_NMI 0x03 |
| 58 | |
Arthur Heymans | e6e5ecb | 2018-12-20 01:44:50 +0100 | [diff] [blame] | 59 | #define FDVCT 0xe4 |
| 60 | #define PCIE_4_PORTS_MAX (1 << 7) |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 61 | #define AHCI_UNSUPPORTED (1 << 3) |
Arthur Heymans | e6e5ecb | 2018-12-20 01:44:50 +0100 | [diff] [blame] | 62 | |
Uwe Hermann | 65ebc79 | 2008-11-06 22:24:05 +0000 | [diff] [blame] | 63 | /* GEN_PMCON_3 bits */ |
| 64 | #define RTC_BATTERY_DEAD (1 << 2) |
| 65 | #define RTC_POWER_FAILED (1 << 1) |
| 66 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 67 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 68 | #define ACPI_CNTL 0x44 |
Kyösti Mälkki | 1cca340 | 2013-02-26 19:21:39 +0200 | [diff] [blame] | 69 | #define ACPI_EN (1 << 7) |
Uwe Hermann | 65ebc79 | 2008-11-06 22:24:05 +0000 | [diff] [blame] | 70 | #define BIOS_CNTL 0xDC |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 71 | #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ |
| 72 | #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ |
Elyes HAOUAS | 32b9a99 | 2019-01-21 14:54:31 +0100 | [diff] [blame] | 73 | #define GPIO_EN (1 << 4) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 74 | |
| 75 | #define PIRQA_ROUT 0x60 |
| 76 | #define PIRQB_ROUT 0x61 |
| 77 | #define PIRQC_ROUT 0x62 |
| 78 | #define PIRQD_ROUT 0x63 |
| 79 | #define PIRQE_ROUT 0x68 |
| 80 | #define PIRQF_ROUT 0x69 |
| 81 | #define PIRQG_ROUT 0x6A |
| 82 | #define PIRQH_ROUT 0x6B |
| 83 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 84 | #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ |
| 85 | #define LPC_EN 0x82 /* LPC IF Enables Register */ |
Damien Zammit | f88b932 | 2015-05-03 18:43:04 +1000 | [diff] [blame] | 86 | #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
| 87 | #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
| 88 | #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
| 89 | #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
| 90 | #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
| 91 | #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
| 92 | #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
| 93 | #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
| 94 | #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
| 95 | #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 96 | |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 97 | #define GEN1_DEC 0x84 |
| 98 | #define GEN2_DEC 0x88 |
| 99 | #define GEN3_DEC 0x8c |
| 100 | #define GEN4_DEC 0x90 |
| 101 | |
Uwe Hermann | 65ebc79 | 2008-11-06 22:24:05 +0000 | [diff] [blame] | 102 | /* PCI Configuration Space (D31:F1): IDE */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 103 | #define INTR_LN 0x3c |
| 104 | #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ |
| 105 | #define IDE_DECODE_ENABLE (1 << 15) |
| 106 | #define IDE_SITRE (1 << 14) |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 107 | #define IDE_ISP_5_CLOCKS (0 << 12) |
| 108 | #define IDE_ISP_4_CLOCKS (1 << 12) |
| 109 | #define IDE_ISP_3_CLOCKS (2 << 12) |
| 110 | #define IDE_RCT_4_CLOCKS (0 << 8) |
| 111 | #define IDE_RCT_3_CLOCKS (1 << 8) |
| 112 | #define IDE_RCT_2_CLOCKS (2 << 8) |
| 113 | #define IDE_RCT_1_CLOCKS (3 << 8) |
| 114 | #define IDE_DTE1 (1 << 7) |
| 115 | #define IDE_PPE1 (1 << 6) |
| 116 | #define IDE_IE1 (1 << 5) |
| 117 | #define IDE_TIME1 (1 << 4) |
| 118 | #define IDE_DTE0 (1 << 3) |
| 119 | #define IDE_PPE0 (1 << 2) |
| 120 | #define IDE_IE0 (1 << 1) |
| 121 | #define IDE_TIME0 (1 << 0) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 122 | #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 123 | |
| 124 | #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ |
| 125 | #define IDE_SSDE1 (1 << 3) |
| 126 | #define IDE_SSDE0 (1 << 2) |
| 127 | #define IDE_PSDE1 (1 << 1) |
| 128 | #define IDE_PSDE0 (1 << 0) |
| 129 | |
| 130 | #define IDE_SDMA_TIM 0x4a |
| 131 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 132 | #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 133 | #define SIG_MODE_SEC_NORMAL (0 << 18) |
| 134 | #define SIG_MODE_SEC_TRISTATE (1 << 18) |
| 135 | #define SIG_MODE_SEC_DRIVELOW (2 << 18) |
| 136 | #define SIG_MODE_PRI_NORMAL (0 << 16) |
| 137 | #define SIG_MODE_PRI_TRISTATE (1 << 16) |
| 138 | #define SIG_MODE_PRI_DRIVELOW (2 << 16) |
| 139 | #define FAST_SCB1 (1 << 15) |
| 140 | #define FAST_SCB0 (1 << 14) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 141 | #define FAST_PCB1 (1 << 13) |
| 142 | #define FAST_PCB0 (1 << 12) |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 143 | #define SCB1 (1 << 3) |
| 144 | #define SCB0 (1 << 2) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 145 | #define PCB1 (1 << 1) |
| 146 | #define PCB0 (1 << 0) |
| 147 | |
Uwe Hermann | 65ebc79 | 2008-11-06 22:24:05 +0000 | [diff] [blame] | 148 | /* PCI Configuration Space (D31:F3): SMBus */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 149 | #define SMB_BASE 0x20 |
| 150 | #define HOSTC 0x40 |
| 151 | |
| 152 | /* HOSTC bits */ |
| 153 | #define I2C_EN (1 << 2) |
| 154 | #define SMB_SMI_EN (1 << 1) |
| 155 | #define HST_EN (1 << 0) |
| 156 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 157 | /* Southbridge IO BARs */ |
| 158 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 159 | #define GPIOBASE 0x48 |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 160 | |
| 161 | #define PMBASE 0x40 |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 162 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 163 | #define VCH 0x0000 /* 32bit */ |
| 164 | #define VCAP1 0x0004 /* 32bit */ |
| 165 | #define VCAP2 0x0008 /* 32bit */ |
| 166 | #define PVC 0x000c /* 16bit */ |
| 167 | #define PVS 0x000e /* 16bit */ |
| 168 | |
| 169 | #define V0CAP 0x0010 /* 32bit */ |
| 170 | #define V0CTL 0x0014 /* 32bit */ |
| 171 | #define V0STS 0x001a /* 16bit */ |
| 172 | |
| 173 | #define V1CAP 0x001c /* 32bit */ |
| 174 | #define V1CTL 0x0020 /* 32bit */ |
| 175 | #define V1STS 0x0026 /* 16bit */ |
| 176 | |
| 177 | #define RCTCL 0x0100 /* 32bit */ |
| 178 | #define ESD 0x0104 /* 32bit */ |
| 179 | #define ULD 0x0110 /* 32bit */ |
| 180 | #define ULBA 0x0118 /* 64bit */ |
| 181 | |
| 182 | #define RP1D 0x0120 /* 32bit */ |
| 183 | #define RP1BA 0x0128 /* 64bit */ |
| 184 | #define RP2D 0x0130 /* 32bit */ |
| 185 | #define RP2BA 0x0138 /* 64bit */ |
| 186 | #define RP3D 0x0140 /* 32bit */ |
| 187 | #define RP3BA 0x0148 /* 64bit */ |
| 188 | #define RP4D 0x0150 /* 32bit */ |
| 189 | #define RP4BA 0x0158 /* 64bit */ |
| 190 | #define HDD 0x0160 /* 32bit */ |
| 191 | #define HDBA 0x0168 /* 64bit */ |
| 192 | #define RP5D 0x0170 /* 32bit */ |
| 193 | #define RP5BA 0x0178 /* 64bit */ |
| 194 | #define RP6D 0x0180 /* 32bit */ |
| 195 | #define RP6BA 0x0188 /* 64bit */ |
| 196 | |
| 197 | #define ILCL 0x01a0 /* 32bit */ |
| 198 | #define LCAP 0x01a4 /* 32bit */ |
| 199 | #define LCTL 0x01a8 /* 16bit */ |
| 200 | #define LSTS 0x01aa /* 16bit */ |
| 201 | |
| 202 | #define RPC 0x0224 /* 32bit */ |
| 203 | #define RPFN 0x0238 /* 32bit */ |
| 204 | |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 205 | /* Get the function number assigned to a Root Port */ |
| 206 | #define RPFN_FNGET(reg, port) (((reg) >> ((port) * 4)) & 7) |
| 207 | /* Set the function number for a Root Port */ |
| 208 | #define RPFN_FNSET(port, func) (((func) & 7) << ((port) * 4)) |
| 209 | /* Root Port function number mask */ |
| 210 | #define RPFN_FNMASK(port) (7 << ((port) * 4)) |
| 211 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 212 | #define TRSR 0x1e00 /* 8bit */ |
| 213 | #define TRCR 0x1e10 /* 64bit */ |
| 214 | #define TWDR 0x1e18 /* 64bit */ |
| 215 | |
| 216 | #define IOTR0 0x1e80 /* 64bit */ |
| 217 | #define IOTR1 0x1e88 /* 64bit */ |
| 218 | #define IOTR2 0x1e90 /* 64bit */ |
| 219 | #define IOTR3 0x1e98 /* 64bit */ |
| 220 | |
| 221 | #define TCTL 0x3000 /* 8bit */ |
| 222 | |
| 223 | #define D31IP 0x3100 /* 32bit */ |
| 224 | #define D30IP 0x3104 /* 32bit */ |
| 225 | #define D29IP 0x3108 /* 32bit */ |
| 226 | #define D28IP 0x310c /* 32bit */ |
| 227 | #define D27IP 0x3110 /* 32bit */ |
| 228 | #define D31IR 0x3140 /* 16bit */ |
| 229 | #define D30IR 0x3142 /* 16bit */ |
| 230 | #define D29IR 0x3144 /* 16bit */ |
| 231 | #define D28IR 0x3146 /* 16bit */ |
| 232 | #define D27IR 0x3148 /* 16bit */ |
| 233 | #define OIC 0x31ff /* 8bit */ |
| 234 | |
| 235 | #define RC 0x3400 /* 32bit */ |
| 236 | #define HPTC 0x3404 /* 32bit */ |
| 237 | #define GCS 0x3410 /* 32bit */ |
| 238 | #define BUC 0x3414 /* 32bit */ |
| 239 | #define FD 0x3418 /* 32bit */ |
| 240 | #define CG 0x341c /* 32bit */ |
| 241 | |
| 242 | /* Function Disable (FD) register values. |
| 243 | * Setting a bit disables the corresponding |
| 244 | * feature. |
| 245 | * Not all features might be disabled on |
| 246 | * all chipsets. Esp. ICH-7U is picky. |
| 247 | */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 248 | #define ICH_DISABLE_PCIE(x) (1 << (16 + (x))) |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 249 | #define FD_EHCI (1 << 15) |
| 250 | #define FD_LPCB (1 << 14) |
| 251 | |
| 252 | /* UHCI must be disabled from 4 downwards. |
| 253 | * If UHCI controllers get disabled, EHCI |
| 254 | * must know about it, too! */ |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 255 | #define ICH_DISABLE_UHCI(x) (1 << (8 + (x))) |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 256 | |
| 257 | #define FD_INTLAN (1 << 7) |
| 258 | #define FD_ACMOD (1 << 6) |
| 259 | #define FD_ACAUD (1 << 5) |
| 260 | #define FD_HDAUD (1 << 4) |
| 261 | #define FD_SMBUS (1 << 3) |
| 262 | #define FD_SATA (1 << 2) |
| 263 | #define FD_PATA (1 << 1) |
| 264 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 265 | /* ICH7 PMBASE */ |
| 266 | #define PM1_STS 0x00 |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 267 | #define WAK_STS (1 << 15) |
| 268 | #define PCIEXPWAK_STS (1 << 14) |
| 269 | #define PRBTNOR_STS (1 << 11) |
| 270 | #define RTC_STS (1 << 10) |
| 271 | #define PWRBTN_STS (1 << 8) |
| 272 | #define GBL_STS (1 << 5) |
| 273 | #define BM_STS (1 << 4) |
| 274 | #define TMROF_STS (1 << 0) |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 275 | #define PM1_EN 0x02 |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 276 | #define PCIEXPWAK_DIS (1 << 14) |
| 277 | #define RTC_EN (1 << 10) |
| 278 | #define PWRBTN_EN (1 << 8) |
| 279 | #define GBL_EN (1 << 5) |
| 280 | #define TMROF_EN (1 << 0) |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 281 | #define PM1_CNT 0x04 |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 282 | #define GBL_RLS (1 << 2) |
| 283 | #define BM_RLD (1 << 1) |
| 284 | #define SCI_EN (1 << 0) |
| 285 | #define PM1_TMR 0x08 |
| 286 | #define PROC_CNT 0x10 |
| 287 | #define LV2 0x14 |
| 288 | #define LV3 0x15 |
| 289 | #define LV4 0x16 |
| 290 | #define PM2_CNT 0x20 // mobile only |
| 291 | #define GPE0_STS 0x28 |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 292 | #define USB4_STS (1 << 14) |
| 293 | #define PME_B0_STS (1 << 13) |
| 294 | #define USB3_STS (1 << 12) |
| 295 | #define PME_STS (1 << 11) |
| 296 | #define BATLOW_STS (1 << 10) |
| 297 | #define PCI_EXP_STS (1 << 9) |
| 298 | #define RI_STS (1 << 8) |
| 299 | #define SMB_WAK_STS (1 << 7) |
| 300 | #define TCOSCI_STS (1 << 6) |
| 301 | #define AC97_STS (1 << 5) |
| 302 | #define USB2_STS (1 << 4) |
| 303 | #define USB1_STS (1 << 3) |
| 304 | #define SWGPE_STS (1 << 2) |
| 305 | #define HOT_PLUG_STS (1 << 1) |
| 306 | #define THRM_STS (1 << 0) |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 307 | #define GPE0_EN 0x2c |
| 308 | #define PME_B0_EN (1 << 13) |
Stefan Reinauer | 7a3d095 | 2010-01-17 13:49:07 +0000 | [diff] [blame] | 309 | #define PME_EN (1 << 11) |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 310 | #define SMI_EN 0x30 |
| 311 | #define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology |
| 312 | #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic |
| 313 | #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic |
| 314 | #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS |
| 315 | #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) |
| 316 | #define MCSMI_EN (1 << 11) // Trap microcontroller range access |
| 317 | #define BIOS_RLS (1 << 7) // asserts SCI on bit set |
| 318 | #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set |
| 319 | #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# |
| 320 | #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# |
| 321 | #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic |
| 322 | #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit |
| 323 | #define EOS (1 << 1) // End of SMI (deassert SMI#) |
| 324 | #define GBL_SMI_EN (1 << 0) // SMI# generation at all? |
| 325 | #define SMI_STS 0x34 |
| 326 | #define ALT_GP_SMI_EN 0x38 |
| 327 | #define ALT_GP_SMI_STS 0x3a |
| 328 | #define GPE_CNTL 0x42 |
| 329 | #define DEVACT_STS 0x44 |
| 330 | #define SS_CNT 0x50 |
| 331 | #define C3_RES 0x54 |
Arthur Heymans | 3664647 | 2018-01-22 14:42:18 +0100 | [diff] [blame] | 332 | #define TCO1_CNT 0x68 |
| 333 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 334 | #endif /* __ACPI__ */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 335 | #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ |