Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 1 | /** |
| 2 | * @file |
| 3 | * |
| 4 | * Config Southbridge GEC controller |
| 5 | * |
| 6 | * Init GEC features. |
| 7 | * |
| 8 | * @xrefitem bom "File Content Label" "Release Content" |
| 9 | * @e project: CIMx-SB |
| 10 | * @e sub-project: |
| 11 | * @e \$Revision:$ @e \$Date:$ |
| 12 | * |
| 13 | */ |
| 14 | /* |
| 15 | ***************************************************************************** |
| 16 | * |
| 17 | * Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 19 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 29 | * from this software without specific prior written permission. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 30 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
Edward O'Callaghan | ef5981b | 2014-07-06 19:20:52 +1000 | [diff] [blame] | 41 | * |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | #include "SBPLATFORM.h" |
| 47 | #include "cbtypes.h" |
| 48 | |
| 49 | /** |
| 50 | * gecInitBeforePciEnum - Config GEC controller before PCI emulation |
| 51 | * |
| 52 | * |
| 53 | * |
| 54 | * @param[in] pConfig Southbridge configuration structure pointer. |
| 55 | * |
| 56 | */ |
| 57 | VOID |
| 58 | gecInitBeforePciEnum ( |
| 59 | IN AMDSBCFG* pConfig |
| 60 | ) |
| 61 | { |
| 62 | UINT8 cimSBGecDebugBus; |
| 63 | UINT8 cimSBGecPwr; |
| 64 | |
| 65 | cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus; |
| 66 | cimSBGecPwr = (UINT8) pConfig->SBGecPwr; |
| 67 | #if SB_CIMx_PARAMETER == 0 |
| 68 | cimSBGecDebugBus = cimSBGecDebugBusDefault; |
| 69 | cimSBGecPwr = cimSBGecPwrDefault; |
| 70 | #endif |
| 71 | if ( pConfig->GecConfig == 0) { |
| 72 | // GEC Enabled |
| 73 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00); |
| 74 | RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00); |
| 75 | RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01); |
| 76 | RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01); |
| 77 | //RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01); |
| 78 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5)); |
| 79 | } else { |
| 80 | // GEC Disabled |
| 81 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0); |
| 82 | return; //return if GEC controller is disabled. |
| 83 | } |
| 84 | if ( cimSBGecDebugBus == 1) { |
| 85 | // GEC Debug Bus Enabled |
| 86 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3); |
| 87 | } else { |
| 88 | // GEC Debug Bus Disabled |
| 89 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00); |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | /** |
| 94 | * gecInitAfterPciEnum - Config GEC controller after PCI emulation |
| 95 | * |
| 96 | * |
| 97 | * |
| 98 | * @param[in] pConfig Southbridge configuration structure pointer. |
| 99 | * |
| 100 | */ |
| 101 | VOID |
| 102 | gecInitAfterPciEnum ( |
| 103 | IN AMDSBCFG* pConfig |
| 104 | ) |
| 105 | { |
| 106 | VOID* GecRomAddress; |
| 107 | VOID* GecShadowRomAddress; |
| 108 | UINT32 ddTemp; |
| 109 | UINT8 dbVar; |
| 110 | UINT8 dbTemp; |
| 111 | if ( pConfig->GecConfig == 0) { |
| 112 | dbVar = 0; |
| 113 | ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); |
| 114 | dbTemp = 0x07; |
| 115 | WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp); |
Aaron Durbin | d907a34 | 2014-01-30 22:20:01 -0600 | [diff] [blame] | 116 | if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) { |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 117 | GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr; |
| 118 | GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase; |
| 119 | AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); |
| 120 | ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp); |
| 121 | ddTemp = ddTemp & 0xFFFFFFF0; |
| 122 | RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29); |
| 123 | } |
| 124 | WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | /** |
| 129 | * gecInitLatePost - Prepare GEC controller to boot to OS. |
| 130 | * |
| 131 | * |
| 132 | * @param[in] pConfig Southbridge configuration structure pointer. |
| 133 | * |
| 134 | */ |
| 135 | VOID |
| 136 | gecInitLatePost ( |
| 137 | IN AMDSBCFG* pConfig |
| 138 | ) |
| 139 | { |
Arthur Heymans | 2fe0126 | 2022-03-23 21:46:17 +0100 | [diff] [blame] | 140 | /* if ( !pConfig->GecConfig == 0) { */ |
| 141 | /* return; //return if GEC controller is disabled. */ |
| 142 | /* } */ |
Frank Vibrans | 2b4c831 | 2011-02-14 18:30:54 +0000 | [diff] [blame] | 143 | } |