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review.coreboot.org / coreboot / 1a010236cf922fc28cfb36b604bdf17a9ea3cb82 / . / src / southbridge / amd / cimx / sb800 / acpi / misc_io.asl
blob: b8296fb0663a76a5049e97836cd69e68351b0505 [file] [log] [blame]
Kyösti Mälkki0d30ddd2021-11-06 09:53:40 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3
4/* Client Management index/data registers */
5OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
6 Field(CMT, ByteAcc, NoLock, Preserve) {
7 CMTI, 8,
8 /* Client Management Data register */
9 G64E, 1,
10 G64O, 1,
11 G32O, 2,
12 , 2,
13 GPSL, 2,
14}
15
16/* GPM Port register */
17OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
18 Field(GPT, ByteAcc, NoLock, Preserve) {
19 GPB0,1,
20 GPB1,1,
21 GPB2,1,
22 GPB3,1,
23 GPB4,1,
24 GPB5,1,
25 GPB6,1,
26 GPB7,1,
27}
28
29/* Flash ROM program enable register */
30OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
31 Field(FRE, ByteAcc, NoLock, Preserve) {
32 , 0x00000006,
33 FLRE, 0x00000001,
34}
35
36/* PM2 index/data registers */
37OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
38 Field(PM2R, ByteAcc, NoLock, Preserve) {
39 PM2I, 0x00000008,
40 PM2D, 0x00000008,
41}
42
43/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */
44OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
45 Field(PIOR, ByteAcc, NoLock, Preserve) {
46 PIOI, 0x00000008,
47 PIOD, 0x00000008,
48}
49IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
50 , 1, /* MiscControl */
51 T1EE, 1,
52 T2EE, 1,
53 Offset(0x01), /* MiscStatus */
54 , 1,
55 T1E, 1,
56 T2E, 1,
57 Offset(0x04), /* SmiWakeUpEventEnable3 */
58 , 7,
59 SSEN, 1,
60 Offset(0x07), /* SmiWakeUpEventStatus3 */
61 , 7,
62 CSSM, 1,
63 Offset(0x10), /* AcpiEnable */
64 , 6,
65 PWDE, 1,
66 Offset(0x1C), /* ProgramIoEnable */
67 , 3,
68 MKME, 1,
69 IO3E, 1,
70 IO2E, 1,
71 IO1E, 1,
72 IO0E, 1,
73 Offset(0x1D), /* IOMonitorStatus */
74 , 3,
75 MKMS, 1,
76 IO3S, 1,
77 IO2S, 1,
78 IO1S, 1,
79 IO0S,1,
80 Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */
81 APEB, 16,
82 Offset(0x36), /* GEvtLevelConfig */
83 , 6,
84 ELC6, 1,
85 ELC7, 1,
86 Offset(0x37), /* GPMLevelConfig0 */
87 , 3,
88 PLC0, 1,
89 PLC1, 1,
90 PLC2, 1,
91 PLC3, 1,
92 PLC8, 1,
93 Offset(0x38), /* GPMLevelConfig1 */
94 , 1,
95 PLC4, 1,
96 PLC5, 1,
97 , 1,
98 PLC6, 1,
99 PLC7, 1,
100 Offset(0x3B), /* PMEStatus1 */
101 GP0S, 1,
102 GM4S, 1,
103 GM5S, 1,
104 APS, 1,
105 GM6S, 1,
106 GM7S, 1,
107 GP2S, 1,
108 STSS, 1,
109 Offset(0x55), /* SoftPciRst */
110 SPRE, 1,
111 , 1,
112 , 1,
113 PNAT, 1,
114 PWMK, 1,
115 PWNS, 1,
116
117 Offset(0x65), /* UsbPMControl */
118 , 4,
119 URRE, 1,
120 Offset(0x68), /* MiscEnable68 */
121 , 3,
122 TMTE, 1,
123 , 1,
124 Offset(0x92), /* GEVENTIN */
125 , 7,
126 E7IS, 1,
127 Offset(0x96), /* GPM98IN */
128 G8IS, 1,
129 G9IS, 1,
130 Offset(0x9A), /* EnhanceControl */
131 ,7,
132 HPDE, 1,
133 Offset(0xA8), /* PIO7654Enable */
134 IO4E, 1,
135 IO5E, 1,
136 IO6E, 1,
137 IO7E, 1,
138 Offset(0xA9), /* PIO7654Status */
139 IO4S, 1,
140 IO5S, 1,
141 IO6S, 1,
142 IO7S, 1,
143}
144
145/* PM1 Event Block
146* First word is PM1_Status, Second word is PM1_Enable
147*/
148OperationRegion(P1EB, SystemIO, APEB, 0x04)
149 Field(P1EB, ByteAcc, NoLock, Preserve) {
150 TMST, 1,
151 , 3,
152 BMST, 1,
153 GBST, 1,
154 Offset(0x01),
155 PBST, 1,
156 , 1,
157 RTST, 1,
158 , 3,
159 PWST, 1,
160 SPWS, 1,
161 Offset(0x02),
162 TMEN, 1,
163 , 4,
164 GBEN, 1,
165 Offset(0x03),
166 PBEN, 1,
167 , 1,
168 RTEN, 1,
169 , 3,
170 PWDA, 1,
171}