| Felix Held | 18c83e1 | 2023-12-12 20:17:15 +0100 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <soc/acpi.h> |
| 4 | #include <soc/amd_pci_int_defs.h> |
| 5 | #include <amdblocks/amd_pci_util.h> |
| 6 | #include <types.h> |
| 7 | |
| 8 | /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is |
| 9 | accessed via I/O ports 0xc00/0xc01. */ |
| 10 | |
| 11 | /* |
| 12 | * This controls the device -> IRQ routing. |
| 13 | * |
| 14 | * Hardcoded IRQs: |
| 15 | * 0: timer < soc/amd/common/acpi/lpc.asl |
| 16 | * 1: i8042 - Keyboard |
| 17 | * 2: cascade |
| 18 | * 8: rtc0 <- soc/amd/common/acpi/lpc.asl |
| 19 | * 9: acpi <- soc/amd/common/acpi/lpc.asl |
| 20 | */ |
| 21 | static const struct fch_irq_routing fch_irq_map[] = { |
| 22 | { PIRQ_A, 12, PIRQ_NC }, |
| 23 | { PIRQ_B, 14, PIRQ_NC }, |
| 24 | { PIRQ_C, 15, PIRQ_NC }, |
| 25 | { PIRQ_D, 12, PIRQ_NC }, |
| 26 | { PIRQ_E, 14, PIRQ_NC }, |
| 27 | { PIRQ_F, 15, PIRQ_NC }, |
| 28 | { PIRQ_G, 12, PIRQ_NC }, |
| 29 | { PIRQ_H, 14, PIRQ_NC }, |
| 30 | |
| 31 | { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, |
| 32 | { PIRQ_GPIO, 11, 11 }, |
| 33 | { PIRQ_I2C0, 10, 10 }, |
| 34 | { PIRQ_I2C1, 7, 7 }, |
| 35 | { PIRQ_I2C2, 6, 6 }, |
| 36 | { PIRQ_I2C3, 5, 5 }, |
| 37 | { PIRQ_UART0, 4, 4 }, |
| 38 | { PIRQ_UART1, 3, 3 }, |
| 39 | |
| 40 | /* The MISC registers are not interrupt numbers */ |
| 41 | { PIRQ_MISC, 0xfa, 0x00 }, |
| 42 | { PIRQ_MISC0, 0x91, 0x00 }, |
| 43 | { PIRQ_HPET_L, 0x00, 0x00 }, |
| 44 | { PIRQ_HPET_H, 0x00, 0x00 }, |
| 45 | }; |
| 46 | |
| 47 | const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) |
| 48 | { |
| 49 | *length = ARRAY_SIZE(fch_irq_map); |
| 50 | return fch_irq_map; |
| 51 | } |