| Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; version 2 of the License. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
| 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | ## |
| 19 | |
| 20 | if BOARD_INTEL_BAKERSPORT_FSP |
| 21 | |
| 22 | config BOARD_SPECIFIC_OPTIONS # dummy |
| 23 | def_bool y |
| 24 | select SOC_INTEL_FSP_BAYTRAIL |
| 25 | select BOARD_ROMSIZE_KB_2048 |
| 26 | select HAVE_ACPI_TABLES |
| 27 | select HAVE_OPTION_TABLE |
| 28 | select OVERRIDE_MRC_CACHE_LOC |
| 29 | select POST_IO |
| Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 30 | select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT |
| 31 | select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT |
| 32 | select DEFAULT_CONSOLE_LOGLEVEL_7 if FSP_PACKAGE_DEFAULT |
| 33 | select TSC_MONOTONIC_TIMER |
| 34 | |
| 35 | config MAINBOARD_DIR |
| 36 | string |
| 37 | default "intel/bayleybay_fsp" |
| 38 | |
| 39 | config INCLUDE_ME |
| 40 | bool |
| 41 | default n |
| 42 | |
| 43 | config LOCK_MANAGEMENT_ENGINE |
| 44 | bool |
| 45 | default n |
| 46 | |
| 47 | config MAINBOARD_PART_NUMBER |
| 48 | string |
| Vladimir Serbinenko | 7411657 | 2014-10-24 19:30:06 +0200 | [diff] [blame] | 49 | default "Bakersport CRB (FSP)" |
| Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 50 | |
| Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 51 | config MAX_CPUS |
| 52 | int |
| 53 | default 16 |
| 54 | |
| 55 | config CACHE_ROM_SIZE_OVERRIDE |
| 56 | hex |
| 57 | default 0x800000 |
| 58 | |
| 59 | config FSP_FILE |
| 60 | string |
| 61 | default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP |
| 62 | |
| 63 | config MRC_CACHE_LOC_OVERRIDE |
| 64 | hex |
| 65 | default 0xfff80000 |
| 66 | depends on ENABLE_FSP_FAST_BOOT |
| 67 | |
| 68 | config CBFS_SIZE |
| 69 | hex |
| 70 | default 0x00200000 |
| 71 | |
| 72 | config DRIVERS_PS2_KEYBOARD |
| 73 | bool |
| 74 | default n |
| 75 | |
| Martin Roth | 3ab015c | 2014-06-12 12:08:26 -0600 | [diff] [blame] | 76 | config ENABLE_FSP_FAST_BOOT |
| 77 | bool |
| 78 | depends on HAVE_FSP_BIN |
| 79 | default y |
| 80 | |
| 81 | config VIRTUAL_ROM_SIZE |
| 82 | hex |
| 83 | depends on ENABLE_FSP_FAST_BOOT |
| 84 | default 0x800000 |
| 85 | |
| 86 | config FSP_PACKAGE_DEFAULT |
| 87 | bool "Configure defaults for the Intel FSP package" |
| 88 | default n |
| 89 | |
| 90 | config VGA_BIOS |
| 91 | bool |
| 92 | default y if FSP_PACKAGE_DEFAULT |
| 93 | |
| 94 | endif # BOARD_INTEL_BAKERSPORT_FSP |