Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 8 | #include "i82801gx.h" |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 9 | #include "sata.h" |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 10 | |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 11 | static void ich_hide_devfn(unsigned int devfn) |
| 12 | { |
| 13 | switch (devfn) { |
| 14 | case PCI_DEVFN(27, 0): /* HD Audio Controller */ |
| 15 | RCBA32_OR(FD, FD_HDAUD); |
| 16 | break; |
| 17 | case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ |
| 18 | case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ |
| 19 | case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ |
| 20 | case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ |
| 21 | case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ |
| 22 | case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ |
| 23 | RCBA32_OR(FD, ICH_DISABLE_PCIE(PCI_FUNC(devfn))); |
| 24 | break; |
| 25 | case PCI_DEVFN(29, 0): /* UHCI #1 */ |
| 26 | case PCI_DEVFN(29, 1): /* UHCI #2 */ |
| 27 | case PCI_DEVFN(29, 2): /* UHCI #3 */ |
| 28 | case PCI_DEVFN(29, 3): /* UHCI #4 */ |
| 29 | RCBA32_OR(FD, ICH_DISABLE_UHCI(PCI_FUNC(devfn))); |
| 30 | break; |
| 31 | case PCI_DEVFN(29, 7): /* EHCI #1 */ |
| 32 | RCBA32_OR(FD, FD_EHCI); |
| 33 | break; |
| 34 | case PCI_DEVFN(30, 2): /* AC Audio */ |
| 35 | RCBA32_OR(FD, FD_ACAUD); |
| 36 | break; |
| 37 | case PCI_DEVFN(30, 3): /* AC Modem */ |
| 38 | RCBA32_OR(FD, FD_ACMOD); |
| 39 | break; |
| 40 | case PCI_DEVFN(31, 0): /* LPC */ |
| 41 | RCBA32_OR(FD, FD_LPCB); |
| 42 | break; |
| 43 | case PCI_DEVFN(31, 1): /* PATA #1 */ |
| 44 | RCBA32_OR(FD, FD_PATA); |
| 45 | break; |
| 46 | case PCI_DEVFN(31, 2): /* SATA #1 */ |
| 47 | RCBA32_OR(FD, FD_SATA); |
| 48 | break; |
| 49 | case PCI_DEVFN(31, 3): /* SMBUS */ |
| 50 | RCBA32_OR(FD, FD_SMBUS); |
| 51 | break; |
| 52 | } |
| 53 | } |
| 54 | |
Elyes HAOUAS | 9966703 | 2018-05-13 12:47:28 +0200 | [diff] [blame] | 55 | void i82801gx_enable(struct device *dev) |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 56 | { |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 57 | u32 reg32; |
| 58 | |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 59 | if (!dev->enabled) { |
| 60 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 61 | |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 62 | /* Ensure memory, io, and bus master are all disabled */ |
| 63 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 64 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 65 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 66 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 67 | |
| 68 | /* Hide this device if possible */ |
| 69 | ich_hide_devfn(dev->path.pci.devfn); |
| 70 | } else { |
| 71 | /* Enable SERR */ |
| 72 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 73 | reg32 |= PCI_COMMAND_SERR; |
| 74 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 75 | |
| 76 | if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) { |
| 77 | printk(BIOS_DEBUG, "Set SATA mode early\n"); |
| 78 | sata_enable(dev); |
| 79 | } |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 80 | } |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 81 | } |
| 82 | |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 83 | static void i82801gx_init(void *chip_info) |
| 84 | { |
| 85 | /* Disable performance counter */ |
| 86 | RCBA32_OR(FD, 1); |
| 87 | } |
| 88 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 89 | struct chip_operations southbridge_intel_i82801gx_ops = { |
| 90 | CHIP_NAME("Intel ICH7/ICH7-M (82801Gx) Series Southbridge") |
Arthur Heymans | 6267f5d | 2018-12-15 23:46:48 +0100 | [diff] [blame] | 91 | .enable_dev = i82801gx_enable, |
| 92 | .init = i82801gx_init, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 93 | }; |