Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Kyösti Mälkki | a1ebbc4 | 2014-10-17 22:33:22 +0300 | [diff] [blame] | 3 | |
| 4 | #include <device/pci_def.h> |
| 5 | #include <device/device.h> |
Elyes HAOUAS | 400f9ca | 2019-06-23 07:01:22 +0200 | [diff] [blame] | 6 | #include <stddef.h> |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 7 | #include <OEM.h> /* SMBUS0_BASE_ADDRESS */ |
Kyösti Mälkki | a1ebbc4 | 2014-10-17 22:33:22 +0300 | [diff] [blame] | 8 | |
| 9 | /* warning: Porting.h includes an open #pragma pack(1) */ |
Stefan Reinauer | 8d29dd1 | 2017-06-26 14:30:39 -0700 | [diff] [blame] | 10 | #include <vendorcode/amd/include/Porting.h> |
Elyes HAOUAS | 19f5ba8 | 2018-10-14 14:52:06 +0200 | [diff] [blame] | 11 | #include <AGESA.h> |
Kyösti Mälkki | a1ebbc4 | 2014-10-17 22:33:22 +0300 | [diff] [blame] | 12 | #include "chip.h" |
| 13 | #include "smbus_spd.h" |
| 14 | |
| 15 | #include <northbridge/amd/agesa/dimmSpd.h> |
| 16 | |
| 17 | /* uncomment for source level debug - GDB gets really confused otherwise. */ |
| 18 | //#pragma optimize ("", off) |
| 19 | |
| 20 | /** |
| 21 | * Read a single SPD byte. If the first byte is being read, set up the |
| 22 | * address and offset. Following bytes auto increment. |
| 23 | */ |
| 24 | static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer, |
| 25 | int offset, int initial_offset) |
| 26 | { |
| 27 | unsigned int status = -1; |
| 28 | UINT64 time_limit; |
| 29 | |
| 30 | /* clear status register */ |
| 31 | __outbyte(iobase + SMBUS_STATUS_REG, 0x1E); |
| 32 | |
| 33 | if (offset == initial_offset) { |
| 34 | /* Clear slave status, set offset, set slave address and start reading */ |
| 35 | __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x3E); |
| 36 | __outbyte(iobase + SMBUS_CONTROL_REG, offset); |
| 37 | __outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT); |
| 38 | __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND); |
| 39 | } else { |
| 40 | /* Issue read command - auto increments to next byte */ |
| 41 | __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND); |
| 42 | } |
| 43 | /* time limit to avoid hanging for unexpected error status */ |
| 44 | time_limit = __rdtsc() + MAX_READ_TSC_COUNT; |
| 45 | while (__rdtsc() <= time_limit) { |
| 46 | status = __inbyte(iobase + SMBUS_STATUS_REG); |
| 47 | if ((status & SMBUS_INTERRUPT_MASK) == 0) |
| 48 | continue; /* SMBusInterrupt not set, keep waiting */ |
| 49 | if ((status & HOSTBUSY_MASK) != 0) |
| 50 | continue; /* HostBusy set, keep waiting */ |
| 51 | break; |
| 52 | } |
| 53 | |
| 54 | if (status != STATUS__COMPLETED_SUCCESSFULLY) |
| 55 | return AGESA_ERROR; |
| 56 | |
| 57 | buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG); |
| 58 | return AGESA_SUCCESS; |
| 59 | } |
| 60 | |
| 61 | static void writePmReg(UINT8 reg, UINT8 data) |
| 62 | { |
| 63 | __outbyte(PMIO_INDEX_REG, reg); |
| 64 | __outbyte(PMIO_DATA_REG, data); |
| 65 | } |
| 66 | |
| 67 | static void setupFch(UINT16 ioBase) |
| 68 | { |
| 69 | /* set up SMBUS - Set to SMBUS 0 & set base address */ |
| 70 | /* For SB800 & Hudson1 to SB900 & Hudson 2/3 */ |
| 71 | writePmReg(SMBUS_BAR_HIGH_BYTE, ioBase >> 8); |
| 72 | writePmReg(SMBUS_BAR_LOW_BYTE, (ioBase & 0xe0) | 1); |
| 73 | |
| 74 | /* set SMBus clock to 400 KHz */ |
| 75 | __outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000); |
| 76 | } |
| 77 | |
| 78 | /** |
| 79 | * Read one or more SPD bytes from a DIMM. |
| 80 | * Start with offset zero and read sequentially. |
| 81 | * Reads 128 bytes in 7-8 ms at 400 KHz. |
| 82 | */ |
| 83 | static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer, |
| 84 | UINT16 count) |
| 85 | { |
| 86 | UINT16 index; |
| 87 | UINT8 status; |
| 88 | UINT8 initial_offset = 0; |
| 89 | |
| 90 | setupFch(iobase); |
| 91 | |
| 92 | for (index = initial_offset; index < count; index++) { |
| 93 | status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index, |
| 94 | initial_offset); |
| 95 | if (status != AGESA_SUCCESS) |
| 96 | return status; |
| 97 | } |
| 98 | |
| 99 | return status; |
| 100 | } |
| 101 | |
| 102 | int smbus_readSpd(int spdAddress, char *buf, size_t len) |
| 103 | { |
| 104 | int ioBase = SMBUS0_BASE_ADDRESS; |
| 105 | setupFch (ioBase); |
| 106 | return readspd (ioBase, spdAddress, buf, len); |
| 107 | } |