blob: 58c2d05a456435edb961060eb3082abb05658aab [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Kyösti Mälkki1fd75082013-06-11 16:32:01 +03003
4// Use simple device model for this file even in ramstage
5#define __SIMPLE_DEVICE__
6
zbao246e84b2012-07-13 18:47:03 +08007#include <stdint.h>
8#include <arch/io.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +02009#include <device/mmio.h>
Kyösti Mälkkie2227a22014-02-05 13:02:55 +020010#include <device/pci_ehci.h>
zbao246e84b2012-07-13 18:47:03 +080011#include <device/pci_def.h>
12#include "hudson.h"
13
Kyösti Mälkki021fa782013-08-16 06:34:04 +030014#define DEBUGPORT_MISC_CONTROL 0x80
zbao246e84b2012-07-13 18:47:03 +080015
Kyösti Mälkki8101aa62013-08-15 16:27:06 +030016pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
zbao246e84b2012-07-13 18:47:03 +080017{
Kyösti Mälkki6683e402017-07-30 13:23:32 +030018 /* Enable all of the USB controllers */
19 outb(0xEF, PM_INDEX);
20 outb(0x7F, PM_DATA);
21
Elyes HAOUASc021ffe2016-09-18 19:18:56 +020022 if (hcd_idx == 3)
Kyösti Mälkkia1179ca2013-09-17 00:12:05 +030023 return PCI_DEV(0, 0x16, 2);
Elyes HAOUASc021ffe2016-09-18 19:18:56 +020024 else if (hcd_idx == 2)
Kyösti Mälkkia1179ca2013-09-17 00:12:05 +030025 return PCI_DEV(0, 0x13, 2);
26 else
27 return PCI_DEV(0, 0x12, 2);
Kyösti Mälkki8101aa62013-08-15 16:27:06 +030028}
29
30void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
31{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080032 u8 *base_regs = pci_ehci_base_regs(dev);
zbao246e84b2012-07-13 18:47:03 +080033 u32 reg32;
34
35 /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
Kyösti Mälkki021fa782013-08-16 06:34:04 +030036 reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL);
zbao246e84b2012-07-13 18:47:03 +080037 reg32 &= ~(0xf << 28);
38 reg32 |= (port << 28);
39 reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
Kevin Paul Herbert4104e6c2015-02-25 00:36:51 -080040 write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
zbao246e84b2012-07-13 18:47:03 +080041}