| Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 3 | |
| 4 | #ifndef AMD_PCI_INT_DEFS_H |
| 5 | #define AMD_PCI_INT_DEFS_H |
| 6 | |
| 7 | /* |
| 8 | * PIRQ and device routing - these define the index |
| 9 | * into the FCH PCI_INTR 0xC00/0xC01 interrupt |
| 10 | * routing table |
| 11 | */ |
| Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 12 | #if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) |
| Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 13 | #define FCH_INT_TABLE_SIZE 0x54 |
| Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 14 | #elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) |
| Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 15 | #define FCH_INT_TABLE_SIZE 0x42 |
| 16 | #endif |
| 17 | |
| 18 | #define PIRQ_NC 0x1F /* Not Used */ |
| 19 | #define PIRQ_A 0x00 /* INT A */ |
| 20 | #define PIRQ_B 0x01 /* INT B */ |
| 21 | #define PIRQ_C 0x02 /* INT C */ |
| 22 | #define PIRQ_D 0x03 /* INT D */ |
| 23 | #define PIRQ_E 0x04 /* INT E */ |
| 24 | #define PIRQ_F 0x05 /* INT F */ |
| 25 | #define PIRQ_G 0x06 /* INT G */ |
| 26 | #define PIRQ_H 0x07 /* INT H */ |
| 27 | #define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ |
| 28 | #define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ |
| 29 | #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ |
| 30 | #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ |
| 31 | #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ |
| 32 | #define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ |
| 33 | #define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ |
| 34 | #define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ |
| 35 | #define PIRQ_SCI 0x10 /* SCI IRQ */ |
| 36 | #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ |
| 37 | #define PIRQ_ASF 0x12 /* ASF */ |
| 38 | #define PIRQ_HDA 0x13 /* HDA 14h.2 */ |
| 39 | #define PIRQ_FC 0x14 /* FC */ |
| 40 | #define PIRQ_GEC 0x15 /* GEC */ |
| 41 | #define PIRQ_PMON 0x16 /* Performance Monitor */ |
| Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 42 | #if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) |
| Kyösti Mälkki | 109a58a | 2019-01-10 10:00:38 +0200 | [diff] [blame] | 43 | #define PIRQ_SD 0x17 /* SD */ |
| Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 44 | #endif |
| 45 | #define PIRQ_IMC0 0x20 /* IMC INT0 */ |
| 46 | #define PIRQ_IMC1 0x21 /* IMC INT1 */ |
| 47 | #define PIRQ_IMC2 0x22 /* IMC INT2 */ |
| 48 | #define PIRQ_IMC3 0x23 /* IMC INT3 */ |
| 49 | #define PIRQ_IMC4 0x24 /* IMC INT4 */ |
| 50 | #define PIRQ_IMC5 0x25 /* IMC INT5 */ |
| 51 | #define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ |
| 52 | #define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ |
| 53 | #define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ |
| 54 | #define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ |
| 55 | #define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ |
| 56 | #define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ |
| 57 | #define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ |
| 58 | #define PIRQ_IDE 0x40 /* IDE 14h.1 */ |
| 59 | #define PIRQ_SATA 0x41 /* SATA 11h.0 */ |
| Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 60 | #if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) |
| Kyösti Mälkki | 109a58a | 2019-01-10 10:00:38 +0200 | [diff] [blame] | 61 | #define PIRQ_SD 0x42 /* SD 14h.7 */ |
| Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 62 | #define PIRQ_GPP0 0x50 /* GPP INT 0 */ |
| 63 | #define PIRQ_GPP1 0x51 /* GPP INT 1 */ |
| 64 | #define PIRQ_GPP2 0x52 /* GPP INT 2 */ |
| 65 | #define PIRQ_GPP3 0x53 /* GPP INT 3 */ |
| 66 | #endif |
| 67 | |
| 68 | #endif /* AMD_PCI_INT_DEFS_H */ |