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review.coreboot.org / coreboot / 8670e829a8f2f6e56c2405333a171c2bc7cd017b / . / src / southbridge / intel / ibexpeak / pch.c
blob: 1b9f51533d6f0e5607361019e0d69bad8d0526a1 [file] [log] [blame]
Arthur Heymansd0310fa2019-10-02 00:21:01 +0200[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
Arthur Heymansd0310fa2019-10-02 00:21:01 +0200[diff] [blame]4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; version 2 of
8 * the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <console/console.h>
17#include <device/pci_ops.h>
18#include <device/device.h>
19#include <device/pci.h>
20#include <device/pci_def.h>
21#include "pch.h"
22
23/* Set bit in function disable register to hide this device */
24static void pch_disable_devfn(struct device *dev)
25{
26 switch (dev->path.pci.devfn) {
27 case PCI_DEVFN(22, 0): /* MEI #1 */
28 RCBA32_OR(FD2, PCH_DISABLE_MEI1);
29 break;
30 case PCI_DEVFN(22, 1): /* MEI #2 */
31 RCBA32_OR(FD2, PCH_DISABLE_MEI2);
32 break;
33 case PCI_DEVFN(22, 2): /* IDE-R */
34 RCBA32_OR(FD2, PCH_DISABLE_IDER);
35 break;
36 case PCI_DEVFN(22, 3): /* KT */
37 RCBA32_OR(FD2, PCH_DISABLE_KT);
38 break;
39 case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
40 RCBA32_OR(BUC, PCH_DISABLE_GBE);
41 break;
42 case PCI_DEVFN(26, 0): /* EHCI #2 */
43 RCBA32_OR(FD, PCH_DISABLE_EHCI2);
44 break;
45 case PCI_DEVFN(27, 0): /* HD Audio Controller */
46 RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
47 break;
48 case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
49 case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
50 case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
51 case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
52 case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
53 case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
54 case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
55 case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
56 RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
57 break;
58 case PCI_DEVFN(29, 0): /* EHCI #1 */
59 RCBA32_OR(FD, PCH_DISABLE_EHCI1);
60 break;
61 case PCI_DEVFN(31, 0): /* LPC */
62 RCBA32_OR(FD, PCH_DISABLE_LPC);
63 break;
64 case PCI_DEVFN(31, 2): /* SATA #1 */
65 RCBA32_OR(FD, PCH_DISABLE_SATA1);
66 break;
67 case PCI_DEVFN(31, 3): /* SMBUS */
68 RCBA32_OR(FD, PCH_DISABLE_SMBUS);
69 break;
70 case PCI_DEVFN(31, 5): /* SATA #22 */
71 RCBA32_OR(FD, PCH_DISABLE_SATA2);
72 break;
73 case PCI_DEVFN(31, 6): /* Thermal Subsystem */
74 RCBA32_OR(FD, PCH_DISABLE_THERMAL);
75 break;
76 }
77}
78
79void pch_enable(struct device *dev)
80{
81 u32 reg32;
82
83 if (!dev->enabled) {
84 printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
85
86 /* Ensure memory, io, and bus master are all disabled */
87 reg32 = pci_read_config32(dev, PCI_COMMAND);
88 reg32 &= ~(PCI_COMMAND_MASTER |
89 PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
90 pci_write_config32(dev, PCI_COMMAND, reg32);
91
92 /* Disable this device if possible */
93 pch_disable_devfn(dev);
94 } else {
95 /* Enable SERR */
96 reg32 = pci_read_config32(dev, PCI_COMMAND);
97 reg32 |= PCI_COMMAND_SERR;
98 pci_write_config32(dev, PCI_COMMAND, reg32);
99 }
100}
101
102struct chip_operations southbridge_intel_ibexpeak_ops = {
103 CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge")
104 .enable_dev = pch_enable,
105};