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Arthur Heymans7b9c1392017-04-09 20:40:39 +02001/*
2 * This file is part of the coreboot project.
3 *
Arthur Heymans7b9c1392017-04-09 20:40:39 +02004 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; version 2 of
8 * the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Kyösti Mälkki13f66502019-03-03 08:01:05 +020016#include <device/mmio.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020017#include <device/pci_ops.h>
Arthur Heymans7b9c1392017-04-09 20:40:39 +020018#include <device/device.h>
19#include <device/pci.h>
20#include <device/pci_ids.h>
21
Arthur Heymans349e0852017-04-09 20:48:37 +020022#include "i82801jx.h"
Arthur Heymans7b9c1392017-04-09 20:40:39 +020023
24static void thermal_init(struct device *dev)
25{
Kyösti Mälkkic70eed12018-05-22 02:18:00 +030026 if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0)))
Arthur Heymans7b9c1392017-04-09 20:40:39 +020027 return;
28
29 u8 reg8;
30 u32 reg32;
31
32 pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR);
33 reg32 = pci_read_config32(dev, 0x04);
34 pci_write_config32(dev, 0x04, reg32 | (1 << 1));
35
36 write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */
37 write32(DEFAULT_TBAR + 0x44, 0);
38
39 write8(DEFAULT_TBAR + 0x01, 0xba); /* Enable sensor 0 + 1. */
40 write8(DEFAULT_TBAR + 0x41, 0xba);
41
42 reg8 = read8(DEFAULT_TBAR + 0x08); /* Lock thermal registers. */
43 write8(DEFAULT_TBAR + 0x08, reg8 | (1 << 7));
44 reg8 = read8(DEFAULT_TBAR + 0x48);
45 write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7));
46
47 reg32 = pci_read_config32(dev, 0x04);
48 pci_write_config32(dev, 0x04, reg32 & ~(1 << 1));
49 pci_write_config32(dev, 0x10, 0);
50}
51
Arthur Heymans7b9c1392017-04-09 20:40:39 +020052static struct pci_operations thermal_pci_ops = {
Subrata Banik4a0f0712019-03-20 14:29:47 +053053 .set_subsystem = pci_dev_set_subsystem,
Arthur Heymans7b9c1392017-04-09 20:40:39 +020054};
55
56static struct device_operations device_ops = {
57 .read_resources = pci_dev_read_resources,
58 .set_resources = pci_dev_set_resources,
59 .enable_resources = pci_dev_enable_resources,
60 .init = thermal_init,
61 .scan_bus = 0,
62 .ops_pci = &thermal_pci_ops,
63};
64
Arthur Heymans349e0852017-04-09 20:48:37 +020065static const unsigned short pci_device_ids[] = {
66 0x3a32,
67 0x3a62,
68 0
69};
70
71static const struct pci_driver ich10_thermal __pci_driver = {
Arthur Heymans7b9c1392017-04-09 20:40:39 +020072 .ops = &device_ops,
73 .vendor = PCI_VENDOR_ID_INTEL,
Arthur Heymans349e0852017-04-09 20:48:37 +020074 .devices = pci_device_ids,
Arthur Heymans7b9c1392017-04-09 20:40:39 +020075};