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zbao246e84b2012-07-13 18:47:03 +08001/*
2 * This file is part of the coreboot project.
3 *
zbao246e84b2012-07-13 18:47:03 +08004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
zbao246e84b2012-07-13 18:47:03 +080013 */
14
zbao246e84b2012-07-13 18:47:03 +080015#include <device/device.h>
zbao246e84b2012-07-13 18:47:03 +080016#include <device/pci.h>
17#include <device/pci_ids.h>
18#include <device/pci_ops.h>
zbao246e84b2012-07-13 18:47:03 +080019
Elyes HAOUASbf0970e2019-03-21 11:10:03 +010020#include "hudson.h"
zbao246e84b2012-07-13 18:47:03 +080021
22static void sata_init(struct device *dev)
23{
Julius Wernercd49cce2019-03-05 16:53:33 -080024#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)
Bruce Griffith37a1d6c2013-07-23 11:50:12 -060025 /**************************************
26 * Configure the SATA port multiplier *
27 **************************************/
28 #define BYTE_TO_DWORD_OFFSET(x) (x/4)
29 #define AHCI_BASE_ADDRESS_REG 0x24
30 #define MISC_CONTROL_REG 0x40
31 #define UNLOCK_BIT (1<<0)
32 #define SATA_CAPABILITIES_REG 0xFC
33 #define CFG_CAP_SPM (1<<12)
34
35 volatile u32 *ahci_ptr =
Stefan Reinauer772029f2015-07-30 16:23:50 -070036 (u32*)(uintptr_t)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00);
Bruce Griffith37a1d6c2013-07-23 11:50:12 -060037 u32 temp;
38
39 /* unlock the write-protect */
40 temp = pci_read_config32(dev, MISC_CONTROL_REG);
41 temp |= UNLOCK_BIT;
42 pci_write_config32(dev, MISC_CONTROL_REG, temp);
43
44 /* set the SATA AHCI mode to allow port expanders */
45 *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM;
46
47 /* lock the write-protect */
48 temp = pci_read_config32(dev, MISC_CONTROL_REG);
49 temp &= ~UNLOCK_BIT;
50 pci_write_config32(dev, MISC_CONTROL_REG, temp);
51#endif
52};
zbao246e84b2012-07-13 18:47:03 +080053
54static struct pci_operations lops_pci = {
55 /* .set_subsystem = pci_dev_set_subsystem, */
56};
57
58static struct device_operations sata_ops = {
59 .read_resources = pci_dev_read_resources,
60 .set_resources = pci_dev_set_resources,
61 .enable_resources = pci_dev_enable_resources,
62 .init = sata_init,
63 .scan_bus = 0,
64 .ops_pci = &lops_pci,
65};
66
67static const struct pci_driver sata0_driver __pci_driver = {
68 .ops = &sata_ops,
69 .vendor = PCI_VENDOR_ID_AMD,
Kyösti Mälkki9d9a5522016-11-19 22:14:59 +020070 .device = PCI_DEVICE_ID_AMD_SB900_SATA,
zbao246e84b2012-07-13 18:47:03 +080071};
Siyuan Wang91571452013-07-09 17:32:42 +080072
73static const struct pci_driver sata0_driver_ahci __pci_driver = {
74 .ops = &sata_ops,
75 .vendor = PCI_VENDOR_ID_AMD,
Kyösti Mälkki9d9a5522016-11-19 22:14:59 +020076 .device = PCI_DEVICE_ID_AMD_SB900_SATA_AHCI,
Siyuan Wang91571452013-07-09 17:32:42 +080077};