| Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame^] | 1 | #include <console/console.h> |
| 2 | #include <device/device.h> |
| 3 | #include <device/pci.h> |
| 4 | #include <device/pci_ids.h> |
| 5 | #include <device/chip.h> |
| 6 | #include "i82801dbm.h" |
| 7 | |
| 8 | void i82801dbm_enable(device_t dev) |
| 9 | { |
| 10 | device_t lpc_dev; |
| 11 | unsigned int index; |
| 12 | uint16_t reg_old, reg; |
| 13 | |
| 14 | // all 82801dbm device ares in bus 0 |
| 15 | unsigned int devfn; |
| 16 | devfn = PCI_DEVFN(0x1f, 0); // lpc |
| 17 | lpc_dev = dev_find_slot(0, devfn); // 0 |
| 18 | if (!lpc_dev ) { |
| 19 | return; |
| 20 | } |
| 21 | #if 0 |
| 22 | if ((lpc_dev->vendor != PCI_VENDOR_ID_INTEL) || |
| 23 | (lpc_dev->device != PCI_DEVICE_ID_INTEL_82801ER_1F0)) { |
| 24 | uint32_t id; |
| 25 | id = pci_read_config32(lpc_dev, PCI_VENDOR_ID); |
| 26 | if (id != (PCI_VENDOR_ID_INTEL | (PCI_DEVICE_ID_INTEL_82801ER_1F0 << 16))) { |
| 27 | return; |
| 28 | } |
| 29 | } |
| 30 | #endif |
| 31 | |
| 32 | index = (dev->path.u.pci.devfn & 7); |
| 33 | if((dev->path.u.pci.devfn & ~0x7)==devfn) { // D=0x1f |
| 34 | if(index==0){ //1f0 |
| 35 | index = 14; |
| 36 | } |
| 37 | } else { // D=0x1d |
| 38 | index += 8; |
| 39 | } |
| 40 | |
| 41 | reg_old = pci_read_config16(lpc_dev, FUNC_DIS); |
| 42 | reg = reg_old; |
| 43 | reg &= ~(1<<index); // enable it |
| 44 | if (!dev->enabled) { |
| 45 | reg |= (1<<index); // disable it |
| 46 | } |
| 47 | if (reg != reg_old) { |
| 48 | pci_write_config16(lpc_dev, FUNC_DIS, reg); |
| 49 | } |
| 50 | reg = pci_read_config16(lpc_dev, FUNC_DIS); |
| 51 | |
| 52 | } |
| 53 | |
| 54 | struct chip_control southbridge_intel_i82801dbm_control = { |
| 55 | .name = "Intel 82801dbm Southbridge", |
| 56 | .enable_dev = i82801dbm_enable, |
| 57 | }; |