Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 16 | #include <arch/acpi.h> |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include <stdint.h> |
| 22 | #include <reg_script.h> |
| 23 | |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 24 | #include <soc/iomap.h> |
| 25 | #include <soc/iosf.h> |
| 26 | #include <soc/lpc.h> |
| 27 | #include <soc/pattrs.h> |
| 28 | #include <soc/pci_devs.h> |
| 29 | #include <soc/pmc.h> |
| 30 | #include <soc/ramstage.h> |
| 31 | #include <soc/xhci.h> |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 32 | |
| 33 | #include "chip.h" |
| 34 | |
| 35 | struct reg_script usb3_phy_script[] = { |
| 36 | /* USB3PHYInit() */ |
| 37 | REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_PLL_CONTROL, |
| 38 | ~0x00700000, 0x00500000), |
| 39 | REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_VCO_START_CAL_POINT, |
| 40 | ~0x001f0000, 0x000A0000), |
| 41 | REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CCDRLF, |
| 42 | ~0x0000000f, 0x0000000b), |
| 43 | REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_PEAKING_AMP_CONFIG_DIAG, |
| 44 | ~0x000000f0, 0x000000f0), |
| 45 | REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_OFFSET_COR_CONFIG_DIAG, |
| 46 | ~0x000001c0, 0x00000000), |
| 47 | REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_VGA_GAIN_CONFIG_DIAG, |
| 48 | ~0x00000070, 0x00000020), |
| 49 | REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_REE_DAC_CONTROL, |
| 50 | ~0x00000002, 0x00000002), |
| 51 | REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_U1_POWER_STATE_DEF, |
| 52 | ~0x00000000, 0x00040000), |
| 53 | REG_SCRIPT_END |
| 54 | }; |
| 55 | |
| 56 | const struct reg_script xhci_init_script[] = { |
| 57 | /* CommonXhciHcInit() */ |
| 58 | /* BAR + 0x0c[31:16] = 0x0200 */ |
| 59 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0x0000ffff, 0x02000000), |
| 60 | /* BAR + 0x0c[7:0] = 0x0a */ |
| 61 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0xffffff00, 0x0000000a), |
| 62 | /* BAR + 0x8094[23,21,14]=111b */ |
| 63 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8094, 0x00a04000), |
| 64 | /* BAR + 0x8110[20,11,8,2]=1100b */ |
| 65 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8110, ~0x00000104, 0x00100800), |
| 66 | /* BAR + 0x8144[8,7,6]=111b */ |
| 67 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8144, 0x000001c0), |
| 68 | /* BAR + 0x8154[21,13,3]=010b */ |
| 69 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8154, ~0x00200008, 0x80002000), |
| 70 | /* BAR + 0x816c[19:0]=1110x100000000111100b */ |
| 71 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x816c, 0xfff08000, 0x000e0030), |
| 72 | /* BAR + 0x8188[26,24]=11b */ |
| 73 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8188, 0x05000000), |
| 74 | /* BAR + 0x8174=0x1000c0a*/ |
| 75 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8174, 0xfe000000, 0x01000c0a), |
| 76 | /* BAR + 0x854c[29]=0b */ |
| 77 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x854c, ~0x20000000, 0), |
| 78 | /* BAR + 0x8178[12:0]=0b */ |
| 79 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8178, ~0xffffe000, 0), |
| 80 | /* BAR + 0x8164[7:0]=0xff */ |
| 81 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8164, 0x000000ff), |
| 82 | /* BAR + 0x0010[10,9,5]=110b */ |
| 83 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0010, ~0x00000020, 0x00000600), |
| 84 | /* BAR + 0x8058[20,16,8]=110b */ |
Duncan Laurie | a90a59f5 | 2013-11-04 11:22:27 -0800 | [diff] [blame] | 85 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 86 | /* BAR + 0x8060[25]=1b */ |
| 87 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 88 | /* BAR + 0x80f0[20]=0b */ |
| 89 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0), |
| 90 | /* BAR + 0x8008[19]=1b (to enable LPM) */ |
| 91 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8008, 0x00080000), |
| 92 | /* BAR + 0x80fc[25]=1b */ |
| 93 | REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x80fc, 0x02000000), |
| 94 | /* 0x40/0x44 are written as bytes to avoid touching bit31 */ |
| 95 | /* D20:F0:40[21,20,18,10,9,8]=111001b (don't write byte3) */ |
| 96 | REG_PCI_RMW8(0x41, ~0x06, 0x01), |
| 97 | /* Except [21,20,19,18]=0001b USB wake W/A is disable IIL1E */ |
| 98 | REG_PCI_RMW8(0x42, 0x3c, 0x04), |
| 99 | /* D20:F0:44[19:14,10,9,7,3:0]=1 (don't write byte3) */ |
| 100 | REG_PCI_RMW8(0x44, 0x00, 0x8f), |
| 101 | REG_PCI_RMW8(0x45, ~0xcf, 0xc6), |
| 102 | REG_PCI_RMW8(0x46, ~0x0f, 0x0f), |
| 103 | /* BAR + 0x8140 = 0xff00f03c */ |
| 104 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8140, 0, 0xff00f03c), |
| 105 | REG_SCRIPT_END |
| 106 | }; |
| 107 | |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 108 | const struct reg_script xhci_init_boot_script[] = { |
| 109 | /* Setup USB3 phy */ |
| 110 | REG_SCRIPT_NEXT(usb3_phy_script), |
| 111 | /* Initialize host controller */ |
| 112 | REG_SCRIPT_NEXT(xhci_init_script), |
| 113 | /* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */ |
| 114 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040), |
| 115 | /* BAR + 0x80e0 toggle bit 24=0 */ |
| 116 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0), |
| 117 | REG_SCRIPT_END |
| 118 | }; |
| 119 | |
| 120 | const struct reg_script xhci_init_resume_script[] = { |
| 121 | /* Setup USB3 phy */ |
| 122 | REG_SCRIPT_NEXT(usb3_phy_script), |
| 123 | /* Initialize host controller */ |
| 124 | REG_SCRIPT_NEXT(xhci_init_script), |
| 125 | /* BAR + 0x80e0[16,9,6]=001b, leave bit 24=0 to prevent HC reset */ |
| 126 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01010200, 0x00000040), |
| 127 | REG_SCRIPT_END |
| 128 | }; |
| 129 | |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 130 | const struct reg_script xhci_clock_gating_script[] = { |
| 131 | /* ConfigureXhciClockGating() */ |
| 132 | /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ |
Duncan Laurie | a90a59f5 | 2013-11-04 11:22:27 -0800 | [diff] [blame] | 133 | REG_PCI_RMW16(0x40, ~0x0600, 0x0100), |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 134 | REG_PCI_RMW8(0x42, ~0x38, 0x04), |
| 135 | /* D20:F0:44[5:3]=001b */ |
| 136 | REG_PCI_RMW16(0x44, ~0x0030, 0x0008), |
| 137 | /* D20:F0:A0[19:18]=01b */ |
| 138 | REG_PCI_RMW32(0xa0, ~0x00080000, 0x00040000), |
| 139 | /* D20:F0:A4[15:0]=0x00 */ |
| 140 | REG_PCI_WRITE16(0xa4, 0x0000), |
| 141 | /* D20:F0:B0[21:17,14:13]=0000000b */ |
| 142 | REG_PCI_RMW32(0xb0, ~0x00376000, 0x00000000), |
| 143 | /* D20:F0:50[31:0]=0x0bce6e5f */ |
| 144 | REG_PCI_WRITE32(0x50, 0x0bce6e5f), |
| 145 | REG_SCRIPT_END |
| 146 | }; |
| 147 | |
| 148 | /* Warm Reset a USB3 port */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame^] | 149 | static void xhci_reset_port_usb3(struct device *dev, int port) |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 150 | { |
| 151 | struct reg_script reset_port_usb3_script[] = { |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 152 | /* Issue Warm Port Rest to the port */ |
| 153 | REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), |
| 154 | XHCI_USB3_PORTSC_WPR), |
| 155 | /* Wait up to 100ms for it to complete */ |
| 156 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), |
| 157 | XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC, |
| 158 | XHCI_RESET_TIMEOUT), |
| 159 | /* Clear change status bits, do not set PED */ |
| 160 | REG_RES_RMW32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), |
| 161 | ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), |
| 162 | REG_SCRIPT_END |
| 163 | }; |
Aaron Durbin | 616f394 | 2013-12-10 17:12:44 -0800 | [diff] [blame] | 164 | reg_script_run_on_dev(dev, reset_port_usb3_script); |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 165 | } |
| 166 | |
| 167 | /* Prepare ports to be routed to EHCI or XHCI */ |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame^] | 168 | static void xhci_route_all(struct device *dev) |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 169 | { |
Aaron Durbin | 616f394 | 2013-12-10 17:12:44 -0800 | [diff] [blame] | 170 | static const struct reg_script xhci_route_all_script[] = { |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 171 | /* USB3 SuperSpeed Enable */ |
| 172 | REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP), |
| 173 | /* USB2 Port Route to XHCI */ |
| 174 | REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP), |
| 175 | REG_SCRIPT_END |
| 176 | }; |
| 177 | u32 port_disabled; |
| 178 | int port; |
| 179 | |
| 180 | printk(BIOS_INFO, "USB: Route ports to XHCI controller\n"); |
| 181 | |
| 182 | /* Route ports to XHCI controller */ |
Aaron Durbin | 616f394 | 2013-12-10 17:12:44 -0800 | [diff] [blame] | 183 | reg_script_run_on_dev(dev, xhci_route_all_script); |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 184 | |
Kyösti Mälkki | 9e94dbf | 2015-01-08 20:03:18 +0200 | [diff] [blame] | 185 | if (acpi_is_wakeup_s3()) |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 186 | return; |
| 187 | |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 188 | /* Reset enabled USB3 ports */ |
| 189 | port_disabled = pci_read_config32(dev, XHCI_USB3PDO); |
| 190 | for (port = 0; port < BYTM_USB3_PORT_COUNT; port++) { |
| 191 | if (port_disabled & (1 << port)) |
| 192 | continue; |
| 193 | xhci_reset_port_usb3(dev, port); |
| 194 | } |
| 195 | } |
| 196 | |
Elyes HAOUAS | 17a3ceb | 2018-05-22 10:42:28 +0200 | [diff] [blame^] | 197 | static void xhci_init(struct device *dev) |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 198 | { |
| 199 | struct soc_intel_baytrail_config *config = dev->chip_info; |
| 200 | struct reg_script xhci_hc_init[] = { |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 201 | /* Initialize clock gating */ |
| 202 | REG_SCRIPT_NEXT(xhci_clock_gating_script), |
Duncan Laurie | a90a59f5 | 2013-11-04 11:22:27 -0800 | [diff] [blame] | 203 | /* Finalize XHCC1 and XHCC2 */ |
| 204 | REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), |
| 205 | REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 206 | /* Set USB2 Port Routing Mask */ |
| 207 | REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), |
| 208 | /* Set USB3 Port Routing Mask */ |
| 209 | REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP), |
| 210 | /* |
| 211 | * Disable ports if requested |
| 212 | */ |
| 213 | /* Open per-port disable control override */ |
| 214 | REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), |
| 215 | REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask), |
| 216 | REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask), |
| 217 | /* Close per-port disable control override */ |
| 218 | REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), |
| 219 | REG_SCRIPT_END |
| 220 | }; |
| 221 | |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 222 | /* Initialize XHCI controller for boot or resume path */ |
Kyösti Mälkki | 9e94dbf | 2015-01-08 20:03:18 +0200 | [diff] [blame] | 223 | if (acpi_is_wakeup_s3()) |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 224 | reg_script_run_on_dev(dev, xhci_init_resume_script); |
| 225 | else |
| 226 | reg_script_run_on_dev(dev, xhci_init_boot_script); |
| 227 | |
Kein Yuan | c9bf446 | 2014-06-27 09:12:57 -0700 | [diff] [blame] | 228 | /* C0 steppings change iCLK/USB PLL VCO settings from 5 to 7 */ |
| 229 | if (pattrs_get()->stepping == STEP_C0) { |
| 230 | uint32_t reg = iosf_ushphy_read(USHPHY_CDN_PLL_CONTROL); |
| 231 | reg |= 0x00700000; |
| 232 | iosf_ushphy_write(USHPHY_CDN_PLL_CONTROL, reg); |
| 233 | } |
| 234 | |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 235 | /* Finalize Initialization */ |
Aaron Durbin | 616f394 | 2013-12-10 17:12:44 -0800 | [diff] [blame] | 236 | reg_script_run_on_dev(dev, xhci_hc_init); |
Duncan Laurie | f81a91a | 2013-11-01 13:32:53 -0700 | [diff] [blame] | 237 | |
| 238 | /* Route all ports to XHCI if requested */ |
| 239 | if (config->usb_route_to_xhci) |
| 240 | xhci_route_all(dev); |
| 241 | } |
| 242 | |
| 243 | static struct device_operations xhci_device_ops = { |
| 244 | .read_resources = pci_dev_read_resources, |
| 245 | .set_resources = pci_dev_set_resources, |
| 246 | .enable_resources = pci_dev_enable_resources, |
| 247 | .init = xhci_init, |
| 248 | .ops_pci = &soc_pci_ops, |
| 249 | }; |
| 250 | |
| 251 | static const struct pci_driver baytrail_xhci __pci_driver = { |
| 252 | .ops = &xhci_device_ops, |
| 253 | .vendor = PCI_VENDOR_ID_INTEL, |
| 254 | .device = XHCI_DEVID |
| 255 | }; |