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review.coreboot.org / coreboot / 1767cd2a698afaf56daa49dc400194eb3d117a63 / . / src / mainboard / google / rex / chromeos.fmd
blob: 3521232ece854f5fb1ea9b0e7bf8cf75eed5ff0f [file] [log] [blame]
Eric Lai03b39232022-05-23 15:32:00 +0800[diff] [blame]1FLASH 32M {
2 SI_ALL 9M {
3 SI_DESC 16K
4 SI_ME
5 }
6 SI_BIOS 23M {
Subrata Banik1767cd22023-02-21 12:35:45 +0530[diff] [blame^]7 RW_SECTION_A 7092K {
8 VBLOCK_A 8K
Eric Lai03b39232022-05-23 15:32:00 +0800[diff] [blame]9 FW_MAIN_A(CBFS)
10 RW_FWID_A 64
Subrata Banik1767cd22023-02-21 12:35:45 +0530[diff] [blame^]11 ME_RW_A(CBFS) 4400K
Eric Lai03b39232022-05-23 15:32:00 +0800[diff] [blame]12 }
Subrata Banik1767cd22023-02-21 12:35:45 +0530[diff] [blame^]13 RW_MISC 152K {
14 RW_ELOG(PRESERVE) 4K
15 RW_SHARED 4K {
16 SHARED_DATA 4K
17 }
18 RW_VPD(PRESERVE) 8K
19 RW_NVRAM(PRESERVE) 8K
Eric Lai03b39232022-05-23 15:32:00 +0800[diff] [blame]20 UNIFIED_MRC_CACHE(PRESERVE) 128K {
21 RECOVERY_MRC_CACHE 64K
22 RW_MRC_CACHE 64K
23 }
Eric Lai03b39232022-05-23 15:32:00 +0800[diff] [blame]24 }
25 # This section starts at the 16M boundary in SPI flash.
26 # MTL does not support a region crossing this boundary,
27 # because the SPI flash is memory-mapped into two non-
28 # contiguous windows.
Subrata Banik1767cd22023-02-21 12:35:45 +0530[diff] [blame^]29 RW_SECTION_B 7092K {
30 VBLOCK_B 8K
Eric Lai03b39232022-05-23 15:32:00 +0800[diff] [blame]31 FW_MAIN_B(CBFS)
32 RW_FWID_B 64
Subrata Banik1767cd22023-02-21 12:35:45 +0530[diff] [blame^]33 ME_RW_B(CBFS) 4400K
Eric Lai03b39232022-05-23 15:32:00 +0800[diff] [blame]34 }
Subrata Banik1767cd22023-02-21 12:35:45 +0530[diff] [blame^]35 RW_LEGACY(CBFS) 1M
Eric Lai03b39232022-05-23 15:32:00 +0800[diff] [blame]36 # Make WP_RO region align with SPI vendor
37 # memory protected range specification.
38 WP_RO 8M {
39 RO_VPD(PRESERVE) 16K
Kapil Porwal381c2192022-07-20 14:22:41 +0000[diff] [blame]40 RO_GSCVD 8K
Eric Lai03b39232022-05-23 15:32:00 +0800[diff] [blame]41 RO_SECTION {
42 FMAP 2K
43 RO_FRID 64
44 GBB@4K 12K
45 COREBOOT(CBFS)
46 }
47 }
48 }
49}