Angel Pons | 16f6aa8 | 2020-04-05 15:47:21 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 3 | |
| 4 | /* |
| 5 | * This file is created based on Intel Tiger Lake Platform Stepping and IDs |
| 6 | * Document number: 605534 |
| 7 | * Chapter number: 2, 4, 5, 6 |
| 8 | */ |
| 9 | |
| 10 | #include <arch/cpu.h> |
| 11 | #include <device/pci_ops.h> |
| 12 | #include <console/console.h> |
| 13 | #include <cpu/x86/msr.h> |
| 14 | #include <device/pci.h> |
| 15 | #include <device/pci_ids.h> |
| 16 | #include <intelblocks/mp_init.h> |
| 17 | #include <soc/bootblock.h> |
| 18 | #include <soc/pch.h> |
| 19 | #include <soc/pci_devs.h> |
| 20 | #include <string.h> |
| 21 | |
| 22 | #define BIOS_SIGN_ID 0x8B |
| 23 | |
Subrata Banik | ae69575 | 2019-11-12 12:47:43 +0530 | [diff] [blame] | 24 | static struct { |
| 25 | u32 cpuid; |
| 26 | const char *name; |
| 27 | } cpu_table[] = { |
| 28 | { CPUID_TIGERLAKE_A0, "Tigerlake A0" }, |
| 29 | }; |
| 30 | |
| 31 | static struct { |
| 32 | u16 mchid; |
| 33 | const char *name; |
| 34 | } mch_table[] = { |
| 35 | { PCI_DEVICE_ID_INTEL_TGL_ID_U, "Tigerlake-U-4-2" }, |
| 36 | { PCI_DEVICE_ID_INTEL_TGL_ID_U_1, "Tigerlake-U-4-3e" }, |
Srinidhi N Kaushik | 1d812e8 | 2020-02-07 15:51:09 -0800 | [diff] [blame] | 37 | { PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2, "Tigerlake-U-2-2" }, |
Subrata Banik | ae69575 | 2019-11-12 12:47:43 +0530 | [diff] [blame] | 38 | { PCI_DEVICE_ID_INTEL_TGL_ID_Y, "Tigerlake-Y-4-2" }, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 39 | { PCI_DEVICE_ID_INTEL_JSL_EHL, "Jasperlake Elkhartlake" }, |
| 40 | { PCI_DEVICE_ID_INTEL_EHL_ID_1, "Elkhartlake-1" }, |
Subrata Banik | ae69575 | 2019-11-12 12:47:43 +0530 | [diff] [blame] | 41 | }; |
| 42 | |
| 43 | static struct { |
| 44 | u16 espiid; |
| 45 | const char *name; |
| 46 | } pch_table[] = { |
| 47 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_0, "Tigerlake-Base SKU" }, |
| 48 | { PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, "Tigerlake-U Super SKU" }, |
| 49 | { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, "Tigerlake-U Premium SKU" }, |
| 50 | { PCI_DEVICE_ID_INTEL_TGP_BASE_U_ESPI, "Tigerlake-U Base SKU" }, |
| 51 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_1, "Tigerlake-Base SKU" }, |
| 52 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_2, "Tigerlake-Base SKU" }, |
| 53 | { PCI_DEVICE_ID_INTEL_TGP_SUPER_Y_ESPI, "Tigerlake-Y Super SKU" }, |
| 54 | { PCI_DEVICE_ID_INTEL_TGP_PREMIUM_Y_ESPI, "Tigerlake-Y Premium SKU" }, |
| 55 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_3, "Tigerlake-Base SKU" }, |
| 56 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_4, "Tigerlake-Base SKU" }, |
| 57 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_5, "Tigerlake-Base SKU" }, |
| 58 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_6, "Tigerlake-Base SKU" }, |
| 59 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_7, "Tigerlake-Base SKU" }, |
| 60 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_8, "Tigerlake-Base SKU" }, |
| 61 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_9, "Tigerlake-Base SKU" }, |
| 62 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_10, "Tigerlake-Base SKU" }, |
| 63 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_11, "Tigerlake-Base SKU" }, |
| 64 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_12, "Tigerlake-Base SKU" }, |
| 65 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_13, "Tigerlake-Base SKU" }, |
| 66 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_14, "Tigerlake-Base SKU" }, |
| 67 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_15, "Tigerlake-Base SKU" }, |
| 68 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_16, "Tigerlake-Base SKU" }, |
| 69 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_17, "Tigerlake-Base SKU" }, |
| 70 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_18, "Tigerlake-Base SKU" }, |
| 71 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_19, "Tigerlake-Base SKU" }, |
| 72 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_20, "Tigerlake-Base SKU" }, |
| 73 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_21, "Tigerlake-Base SKU" }, |
| 74 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_22, "Tigerlake-Base SKU" }, |
| 75 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_23, "Tigerlake-Base SKU" }, |
| 76 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_24, "Tigerlake-Base SKU" }, |
| 77 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_25, "Tigerlake-Base SKU" }, |
| 78 | { PCI_DEVICE_ID_INTEL_TGP_ESPI_26, "Tigerlake-Base SKU" }, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 79 | { PCI_DEVICE_ID_INTEL_MCC_ESPI_0, "Elkhartlake-0" }, |
| 80 | { PCI_DEVICE_ID_INTEL_MCC_ESPI_1, "Elkhartlake-1" }, |
| 81 | { PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" }, |
| 82 | { PCI_DEVICE_ID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" }, |
| 83 | { PCI_DEVICE_ID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" }, |
Subrata Banik | ae69575 | 2019-11-12 12:47:43 +0530 | [diff] [blame] | 84 | }; |
| 85 | |
| 86 | static struct { |
| 87 | u16 igdid; |
| 88 | const char *name; |
| 89 | } igd_table[] = { |
| 90 | { PCI_DEVICE_ID_INTEL_TGL_GT0, "Tigerlake U GT0" }, |
| 91 | { PCI_DEVICE_ID_INTEL_TGL_GT2_ULT, "Tigerlake U GT2" }, |
| 92 | { PCI_DEVICE_ID_INTEL_TGL_GT2_ULX, "Tigerlake Y GT2" }, |
| 93 | { PCI_DEVICE_ID_INTEL_TGL_GT3_ULT, "Tigerlake U GT3" }, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 94 | { PCI_DEVICE_ID_INTEL_EHL_GT1_1, "Elkhartlake GT1 1" }, |
| 95 | { PCI_DEVICE_ID_INTEL_EHL_GT2_1, "Elkhartlake GT2 1" }, |
| 96 | { PCI_DEVICE_ID_INTEL_EHL_GT1_2, "Elkhartlake GT1 2" }, |
| 97 | { PCI_DEVICE_ID_INTEL_EHL_GT2_2, "Elkhartlake GT2 2" }, |
| 98 | { PCI_DEVICE_ID_INTEL_EHL_GT1_3, "Elkhartlake GT1 3" }, |
| 99 | { PCI_DEVICE_ID_INTEL_EHL_GT2_3, "Elkhartlake GT2 3" }, |
Subrata Banik | ae69575 | 2019-11-12 12:47:43 +0530 | [diff] [blame] | 100 | }; |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 101 | |
| 102 | static inline uint8_t get_dev_revision(pci_devfn_t dev) |
| 103 | { |
| 104 | return pci_read_config8(dev, PCI_REVISION_ID); |
| 105 | } |
| 106 | |
| 107 | static inline uint16_t get_dev_id(pci_devfn_t dev) |
| 108 | { |
| 109 | return pci_read_config16(dev, PCI_DEVICE_ID); |
| 110 | } |
| 111 | |
| 112 | static void report_cpu_info(void) |
| 113 | { |
| 114 | struct cpuid_result cpuidr; |
| 115 | u32 i, index, cpu_id, cpu_feature_flag; |
| 116 | const char cpu_not_found[] = "Platform info not available"; |
| 117 | const char *cpu_name = cpu_not_found; /* 48 bytes are reported */ |
| 118 | int vt, txt, aes; |
| 119 | msr_t microcode_ver; |
| 120 | static const char *const mode[] = {"NOT ", ""}; |
| 121 | const char *cpu_type = "Unknown"; |
| 122 | u32 p[13]; |
| 123 | |
| 124 | index = 0x80000000; |
| 125 | cpuidr = cpuid(index); |
| 126 | if (cpuidr.eax >= 0x80000004) { |
| 127 | int j = 0; |
| 128 | |
| 129 | for (i = 2; i <= 4; i++) { |
| 130 | cpuidr = cpuid(index + i); |
| 131 | p[j++] = cpuidr.eax; |
| 132 | p[j++] = cpuidr.ebx; |
| 133 | p[j++] = cpuidr.ecx; |
| 134 | p[j++] = cpuidr.edx; |
| 135 | } |
| 136 | p[12] = 0; |
| 137 | cpu_name = (char *)p; |
| 138 | |
| 139 | /* Skip leading spaces in CPU name string */ |
| 140 | while (cpu_name[0] == ' ' && strlen(cpu_name) > 0) |
| 141 | cpu_name++; |
| 142 | } |
| 143 | |
| 144 | microcode_ver.lo = 0; |
| 145 | microcode_ver.hi = 0; |
| 146 | wrmsr(BIOS_SIGN_ID, microcode_ver); |
| 147 | cpu_id = cpu_get_cpuid(); |
| 148 | microcode_ver = rdmsr(BIOS_SIGN_ID); |
| 149 | |
| 150 | /* Look for string to match the name */ |
| 151 | for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { |
| 152 | if (cpu_table[i].cpuid == cpu_id) { |
| 153 | cpu_type = cpu_table[i].name; |
| 154 | break; |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); |
| 159 | printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", |
| 160 | cpu_id, cpu_type, microcode_ver.hi); |
| 161 | |
| 162 | cpu_feature_flag = cpu_get_feature_flags_ecx(); |
| 163 | aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; |
| 164 | txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; |
| 165 | vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; |
| 166 | printk(BIOS_DEBUG, |
| 167 | "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", |
| 168 | mode[aes], mode[txt], mode[vt]); |
| 169 | } |
| 170 | |
| 171 | static void report_mch_info(void) |
| 172 | { |
| 173 | int i; |
| 174 | pci_devfn_t dev = SA_DEV_ROOT; |
| 175 | uint16_t mchid = get_dev_id(dev); |
| 176 | uint8_t mch_revision = get_dev_revision(dev); |
| 177 | const char *mch_type = "Unknown"; |
| 178 | |
| 179 | for (i = 0; i < ARRAY_SIZE(mch_table); i++) { |
| 180 | if (mch_table[i].mchid == mchid) { |
| 181 | mch_type = mch_table[i].name; |
| 182 | break; |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", |
| 187 | mchid, mch_revision, mch_type); |
| 188 | } |
| 189 | |
| 190 | static void report_pch_info(void) |
| 191 | { |
| 192 | int i; |
| 193 | pci_devfn_t dev = PCH_DEV_ESPI; |
| 194 | uint16_t espiid = get_dev_id(dev); |
| 195 | const char *pch_type = "Unknown"; |
| 196 | |
| 197 | for (i = 0; i < ARRAY_SIZE(pch_table); i++) { |
| 198 | if (pch_table[i].espiid == espiid) { |
| 199 | pch_type = pch_table[i].name; |
| 200 | break; |
| 201 | } |
| 202 | } |
| 203 | printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", |
| 204 | espiid, get_dev_revision(dev), pch_type); |
| 205 | } |
| 206 | |
| 207 | static void report_igd_info(void) |
| 208 | { |
| 209 | int i; |
| 210 | pci_devfn_t dev = SA_DEV_IGD; |
| 211 | uint16_t igdid = get_dev_id(dev); |
| 212 | const char *igd_type = "Unknown"; |
| 213 | |
| 214 | for (i = 0; i < ARRAY_SIZE(igd_table); i++) { |
| 215 | if (igd_table[i].igdid == igdid) { |
| 216 | igd_type = igd_table[i].name; |
| 217 | break; |
| 218 | } |
| 219 | } |
| 220 | printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", |
| 221 | igdid, get_dev_revision(dev), igd_type); |
| 222 | } |
| 223 | |
| 224 | void report_platform_info(void) |
| 225 | { |
| 226 | report_cpu_info(); |
| 227 | report_mch_info(); |
| 228 | report_pch_info(); |
| 229 | report_igd_info(); |
| 230 | } |