Morgan Tsai | 1602dd5 | 2007-10-29 21:00:14 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the LinuxBIOS project. |
| 3 | * |
| 4 | * Copyright (C) 2006 AMD |
| 5 | * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD. |
| 6 | * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS) |
| 7 | * Written by Morgan Tsai <my_tsai@sis.com> for SiS. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 22 | */ |
| 23 | |
| 24 | static int set_ht_link_sis966(uint8_t ht_c_num) |
| 25 | { |
| 26 | unsigned vendorid = 0x10de; |
| 27 | unsigned val = 0x01610109; |
| 28 | /* Nvidia sis966 hardcode, hw can not set it automatically */ |
| 29 | return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val); |
| 30 | } |
| 31 | |
| 32 | static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max) |
| 33 | { |
| 34 | int i; |
| 35 | |
| 36 | unsigned val; |
| 37 | |
| 38 | val = inl(control); |
| 39 | val &= 0xfffffffe; |
| 40 | outl(val, control); |
| 41 | |
| 42 | outl(0, index); //index |
| 43 | for(i = 0; i < max; i++) { |
| 44 | unsigned long reg; |
| 45 | reg = register_values[i]; |
| 46 | outl(reg, where); |
| 47 | } |
| 48 | |
| 49 | val = inl(control); |
| 50 | val |= 1; |
| 51 | outl(val, control); |
| 52 | |
| 53 | } |
| 54 | |
| 55 | /* SIZE 0x100 */ |
| 56 | #define ANACTRL_IO_BASE 0x2800 |
| 57 | #define ANACTRL_REG_POS 0x68 |
| 58 | |
| 59 | /* SIZE 0x100 */ |
| 60 | #define SYSCTRL_IO_BASE 0x2400 |
| 61 | #define SYSCTRL_REG_POS 0x64 |
| 62 | |
| 63 | /* SIZE 0x100 */ |
| 64 | #define ACPICTRL_IO_BASE 0x2000 |
| 65 | #define ACPICTRL_REG_POS 0x60 |
| 66 | |
| 67 | /* |
| 68 | 16 1 1 1 1 8 :0 |
| 69 | 16 0 4 0 0 8 :1 |
| 70 | 16 0 4 2 2 4 :2 |
| 71 | 4 4 4 4 4 8 :3 |
| 72 | 8 8 4 0 0 8 :4 |
| 73 | 8 0 4 4 4 8 :5 |
| 74 | */ |
| 75 | |
| 76 | #ifndef SIS966_PCI_E_X_0 |
| 77 | #define SIS966_PCI_E_X_0 4 |
| 78 | #endif |
| 79 | #ifndef SIS966_PCI_E_X_1 |
| 80 | #define SIS966_PCI_E_X_1 4 |
| 81 | #endif |
| 82 | #ifndef SIS966_PCI_E_X_2 |
| 83 | #define SIS966_PCI_E_X_2 4 |
| 84 | #endif |
| 85 | #ifndef SIS966_PCI_E_X_3 |
| 86 | #define SIS966_PCI_E_X_3 4 |
| 87 | #endif |
| 88 | |
| 89 | #ifndef SIS966_USE_NIC |
| 90 | #define SIS966_USE_NIC 0 |
| 91 | #endif |
| 92 | |
| 93 | #ifndef SIS966_USE_AZA |
| 94 | #define SIS966_USE_AZA 0 |
| 95 | #endif |
| 96 | |
| 97 | #define SIS966_CHIP_REV 3 |
| 98 | |
| 99 | static void sis966_early_set_port(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base) |
| 100 | { |
| 101 | |
| 102 | static const unsigned int ctrl_devport_conf[] = { |
| 103 | PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE, |
| 104 | PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE, |
| 105 | PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE, |
| 106 | }; |
| 107 | |
| 108 | int j; |
| 109 | for(j = 0; j < sis966_num; j++ ) { |
| 110 | setup_resource_map_offset(ctrl_devport_conf, |
| 111 | sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]), |
| 112 | PCI_DEV(busn[j], devn[j], 0) , io_base[j]); |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | static void sis966_early_clear_port(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base) |
| 117 | { |
| 118 | |
| 119 | static const unsigned int ctrl_devport_conf_clear[] = { |
| 120 | PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0, |
| 121 | PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0, |
| 122 | PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0, |
| 123 | }; |
| 124 | |
| 125 | int j; |
| 126 | for(j = 0; j < sis966_num; j++ ) { |
| 127 | setup_resource_map_offset(ctrl_devport_conf_clear, |
| 128 | sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]), |
| 129 | PCI_DEV(busn[j], devn[j], 0) , io_base[j]); |
| 130 | } |
| 131 | |
| 132 | |
| 133 | } |
| 134 | static void delayx(uint8_t value) { |
| 135 | #if 1 |
| 136 | int i; |
| 137 | for(i=0;i<0x8000;i++) { |
| 138 | outb(value, 0x80); |
| 139 | } |
| 140 | #endif |
| 141 | } |
| 142 | |
| 143 | static void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) |
| 144 | { |
| 145 | uint32_t tgio_ctrl; |
| 146 | uint32_t pll_ctrl; |
| 147 | uint32_t dword; |
| 148 | int i; |
| 149 | device_t dev; |
| 150 | dev = PCI_DEV(busnx, devnx+1, 1); |
| 151 | dword = pci_read_config32(dev, 0xe4); |
| 152 | dword |= 0x3f0; // disable it at first |
| 153 | pci_write_config32(dev, 0xe4, dword); |
| 154 | |
| 155 | for(i=0; i<3; i++) { |
| 156 | tgio_ctrl = inl(anactrl_io_base + 0xcc); |
| 157 | tgio_ctrl &= ~(3<<9); |
| 158 | tgio_ctrl |= (i<<9); |
| 159 | outl(tgio_ctrl, anactrl_io_base + 0xcc); |
| 160 | pll_ctrl = inl(anactrl_io_base + 0x30); |
| 161 | pll_ctrl |= (1<<31); |
| 162 | outl(pll_ctrl, anactrl_io_base + 0x30); |
| 163 | do { |
| 164 | pll_ctrl = inl(anactrl_io_base + 0x30); |
| 165 | } while (!(pll_ctrl & 1)); |
| 166 | } |
| 167 | tgio_ctrl = inl(anactrl_io_base + 0xcc); |
| 168 | tgio_ctrl &= ~((7<<4)|(1<<8)); |
| 169 | tgio_ctrl |= (pci_e_x<<4)|(1<<8); |
| 170 | outl(tgio_ctrl, anactrl_io_base + 0xcc); |
| 171 | |
| 172 | // wait 100us |
| 173 | delayx(1); |
| 174 | |
| 175 | dword = pci_read_config32(dev, 0xe4); |
| 176 | dword &= ~(0x3f0); // enable |
| 177 | pci_write_config32(dev, 0xe4, dword); |
| 178 | |
| 179 | // need to wait 100ms |
| 180 | delayx(1000); |
| 181 | } |
| 182 | |
| 183 | static void sis966_early_setup(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x) |
| 184 | { |
| 185 | |
| 186 | static const unsigned int ctrl_conf_1[] = { |
| 187 | RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000, |
| 188 | RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000, |
| 189 | RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200, |
| 190 | RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002, |
| 191 | |
| 192 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230, |
| 193 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222, |
| 194 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000, |
| 195 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000, |
| 196 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000, |
| 197 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, |
| 198 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200, |
| 199 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, |
| 200 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400, |
| 201 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000, |
| 202 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000, |
| 203 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010, |
| 204 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500, |
| 205 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000, |
| 206 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000, |
| 207 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00, |
| 208 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000, |
| 209 | |
| 210 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 211 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002, |
| 212 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011, |
| 213 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923, |
| 214 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000, |
| 215 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F, |
| 216 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000, |
| 217 | |
| 218 | RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 219 | RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084, |
| 220 | RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010, |
| 221 | |
| 222 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001, |
| 223 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002, |
| 224 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010, |
| 225 | |
| 226 | RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 227 | RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF, |
| 228 | RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode |
| 229 | |
| 230 | RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 231 | RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF, |
| 232 | RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode |
| 233 | }; |
| 234 | |
| 235 | static const unsigned int ctrl_conf_1_1[] = { |
| 236 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 237 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003, |
| 238 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001, |
| 239 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000, |
| 240 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100, |
| 241 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000, |
| 242 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A, |
| 243 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000, |
| 244 | RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000, |
| 245 | }; |
| 246 | |
| 247 | |
| 248 | static const unsigned int ctrl_conf_sis966_only[] = { |
| 249 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE, |
| 250 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000, |
| 251 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000, |
| 252 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000, |
| 253 | |
| 254 | // RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 255 | // RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010, |
| 256 | |
| 257 | RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE, |
| 258 | |
| 259 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE, |
| 260 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000, |
| 261 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000, |
| 262 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00, |
| 263 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000, |
| 264 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570, |
| 265 | RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010, |
| 266 | |
| 267 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104, |
| 268 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000, |
| 269 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000, |
| 270 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005, |
| 271 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000, |
| 272 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000, |
| 273 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE, |
| 274 | RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007, |
| 275 | |
| 276 | #if SIS966_USE_AZA == 1 |
| 277 | RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE, |
| 278 | |
| 279 | // RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14, |
| 280 | #endif |
| 281 | // play a while with GPIO in SIS966 |
| 282 | #ifdef SIS966_MB_SETUP |
| 283 | SIS966_MB_SETUP |
| 284 | #endif |
| 285 | |
| 286 | #if SIS966_USE_AZA == 1 |
| 287 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2), |
| 288 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2), |
| 289 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2), |
| 290 | #endif |
| 291 | |
| 292 | |
| 293 | }; |
| 294 | |
| 295 | static const unsigned int ctrl_conf_master_only[] = { |
| 296 | |
| 297 | RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000, |
| 298 | |
| 299 | RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000, |
| 300 | |
| 301 | //Master SIS966 ????YHLU |
| 302 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2), |
| 303 | |
| 304 | }; |
| 305 | |
| 306 | static const unsigned int ctrl_conf_2[] = { |
| 307 | /* I didn't put pcie related stuff here */ |
| 308 | |
| 309 | RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0, |
| 310 | RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000, |
| 311 | |
| 312 | RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000, |
| 313 | |
| 314 | RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012, |
| 315 | |
| 316 | |
| 317 | #if SIS966_USE_NIC == 1 |
| 318 | RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20), |
| 319 | |
| 320 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(0<<0)), |
| 321 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(1<<0)), |
| 322 | #endif |
| 323 | |
| 324 | }; |
| 325 | |
| 326 | |
| 327 | int j, i; |
| 328 | |
| 329 | for(j=0; j<sis966_num; j++) { |
| 330 | sis966_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]); |
| 331 | |
| 332 | setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]), |
| 333 | PCI_DEV(busn[j], devn[j], 0), io_base[j]); |
| 334 | for(i=0; i<3; i++) { // three SATA |
| 335 | setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]), |
| 336 | PCI_DEV(busn[j], devn[j], i), io_base[j]); |
| 337 | } |
| 338 | if(busn[j] == 0) { |
| 339 | setup_resource_map_x_offset(ctrl_conf_sis966_only, sizeof(ctrl_conf_sis966_only)/sizeof(ctrl_conf_sis966_only[0]), |
| 340 | PCI_DEV(busn[j], devn[j], 0), io_base[j]); |
| 341 | } |
| 342 | |
| 343 | if( (busn[j] == 0) && (sis966_num>1) ) { |
| 344 | setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]), |
| 345 | PCI_DEV(busn[j], devn[j], 0), io_base[j]); |
| 346 | } |
| 347 | |
| 348 | setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]), |
| 349 | PCI_DEV(busn[j], devn[j], 0), io_base[j]); |
| 350 | |
| 351 | } |
| 352 | |
| 353 | #if 0 |
| 354 | for(j=0; j< sis966_num; j++) { |
| 355 | // PCI-E (XSPLL) SS table 0x40, x044, 0x48 |
| 356 | // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8 |
| 357 | // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8 |
| 358 | setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44, |
| 359 | io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64); |
| 360 | setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4, |
| 361 | io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64); |
| 362 | setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4, |
| 363 | io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64); |
| 364 | } |
| 365 | #endif |
| 366 | |
| 367 | } |
| 368 | |
| 369 | #ifndef HT_CHAIN_NUM_MAX |
| 370 | |
| 371 | #define HT_CHAIN_NUM_MAX 4 |
| 372 | #define HT_CHAIN_BUSN_D 0x40 |
| 373 | #define HT_CHAIN_IOBASE_D 0x4000 |
| 374 | |
| 375 | #endif |
| 376 | |
| 377 | static int sis966_early_setup_x(void) |
| 378 | { |
| 379 | /*find out how many sis966 we have */ |
| 380 | unsigned busn[HT_CHAIN_NUM_MAX]; |
| 381 | unsigned devn[HT_CHAIN_NUM_MAX]; |
| 382 | unsigned io_base[HT_CHAIN_NUM_MAX]; |
| 383 | /* |
| 384 | FIXME: May have problem if there is different SIS966 HTX card with different PCI_E lane allocation |
| 385 | Need to use same trick about pci1234 to verify node/link connection |
| 386 | */ |
| 387 | unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {SIS966_PCI_E_X_0, SIS966_PCI_E_X_1, SIS966_PCI_E_X_2, SIS966_PCI_E_X_3 }; |
| 388 | int sis966_num = 0; |
| 389 | unsigned busnx; |
| 390 | unsigned devnx; |
| 391 | int ht_c_index,j; |
| 392 | |
| 393 | /* FIXME: multi pci segment handling */ |
| 394 | |
| 395 | /* Any system that only have IO55 without SIS966? */ |
| 396 | for(ht_c_index = 0; ht_c_index<HT_CHAIN_NUM_MAX; ht_c_index++) { |
| 397 | busnx = ht_c_index * HT_CHAIN_BUSN_D; |
| 398 | for(devnx=0;devnx<0x20;devnx++) { |
| 399 | uint32_t id; |
| 400 | device_t dev; |
| 401 | dev = PCI_DEV(busnx, devnx, 0); |
| 402 | id = pci_read_config32(dev, PCI_VENDOR_ID); |
| 403 | if(id == 0x036910de) { |
| 404 | busn[sis966_num] = busnx; |
| 405 | devn[sis966_num] = devnx; |
| 406 | io_base[sis966_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than SIS966 |
| 407 | sis966_num++; |
| 408 | if(sis966_num == SIS966_NUM) goto out; |
| 409 | break; // only one SIS966 on one chain |
| 410 | } |
| 411 | } |
| 412 | } |
| 413 | |
| 414 | out: |
| 415 | print_debug("sis966_num:"); print_debug_hex8(sis966_num); print_debug("\r\n"); |
| 416 | |
| 417 | //sis966_early_set_port(sis966_num, busn, devn, io_base); |
| 418 | //sis966_early_setup(sis966_num, busn, devn, io_base, pci_e_x); |
| 419 | |
| 420 | //sis966_early_clear_port(sis966_num, busn, devn, io_base); |
| 421 | |
| 422 | // set_ht_link_sis966(HT_CHAIN_NUM_MAX); |
| 423 | |
| 424 | return 0; |
| 425 | |
| 426 | } |
| 427 | |
| 428 | |
| 429 | |