Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011-2013 Alexandru Gagniuc <mr.nuke.me@gmail.com> |
| 5 | * |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /** |
Martin Roth | 98b698c | 2015-01-06 21:02:52 -0700 | [diff] [blame] | 18 | * @file ddr3.c |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 19 | * |
| 20 | * \brief Utilities for decoding DDR3 SPDs |
| 21 | */ |
| 22 | |
| 23 | #include <console/console.h> |
| 24 | #include <device/device.h> |
| 25 | #include <device/dram/ddr3.h> |
Patrick Rudolph | 0769159 | 2016-02-29 18:21:00 +0100 | [diff] [blame] | 26 | #include <string.h> |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 27 | |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 28 | /*============================================================================== |
| 29 | * = DDR3 SPD decoding helpers |
| 30 | *----------------------------------------------------------------------------*/ |
| 31 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 32 | /** |
| 33 | * \brief Checks if the DIMM is Registered based on byte[3] of the SPD |
| 34 | * |
| 35 | * Tells if the DIMM type is registered or not. |
| 36 | * |
| 37 | * @param type DIMM type. This is byte[3] of the SPD. |
| 38 | */ |
Patrick Rudolph | 6e53ae6 | 2017-01-31 19:43:17 +0100 | [diff] [blame] | 39 | int spd_dimm_is_registered_ddr3(enum spd_dimm_type type) |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 40 | { |
| 41 | if ((type == SPD_DIMM_TYPE_RDIMM) |
| 42 | | (type == SPD_DIMM_TYPE_MINI_RDIMM) |
| 43 | | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) |
| 44 | return 1; |
| 45 | |
| 46 | return 0; |
| 47 | } |
| 48 | |
Arthur Heymans | 97b337b | 2018-01-22 01:26:53 +0100 | [diff] [blame] | 49 | u16 ddr3_crc16(const u8 *ptr, int n_crc) |
Kyösti Mälkki | 7dc4b84 | 2016-11-18 18:41:17 +0200 | [diff] [blame] | 50 | { |
| 51 | int i; |
| 52 | u16 crc = 0; |
| 53 | |
| 54 | while (--n_crc >= 0) { |
Kyösti Mälkki | 378d79e | 2016-11-21 02:39:59 +0200 | [diff] [blame] | 55 | crc = crc ^ ((int)*ptr++ << 8); |
Kyösti Mälkki | 7dc4b84 | 2016-11-18 18:41:17 +0200 | [diff] [blame] | 56 | for (i = 0; i < 8; ++i) |
| 57 | if (crc & 0x8000) { |
| 58 | crc = (crc << 1) ^ 0x1021; |
| 59 | } else { |
| 60 | crc = crc << 1; |
| 61 | } |
| 62 | } |
| 63 | |
| 64 | return crc; |
| 65 | } |
| 66 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 67 | /** |
Alexandru Gagniuc | 4c37e58 | 2013-12-17 13:08:01 -0500 | [diff] [blame] | 68 | * \brief Calculate the CRC of a DDR3 SPD |
| 69 | * |
| 70 | * @param spd pointer to raw SPD data |
| 71 | * @param len length of data in SPD |
| 72 | * |
| 73 | * @return the CRC of the SPD data, or 0 when spd data is truncated. |
| 74 | */ |
| 75 | u16 spd_ddr3_calc_crc(u8 *spd, int len) |
| 76 | { |
Kyösti Mälkki | 7dc4b84 | 2016-11-18 18:41:17 +0200 | [diff] [blame] | 77 | int n_crc; |
Alexandru Gagniuc | 4c37e58 | 2013-12-17 13:08:01 -0500 | [diff] [blame] | 78 | |
| 79 | /* Find the number of bytes covered by CRC */ |
| 80 | if (spd[0] & 0x80) { |
| 81 | n_crc = 117; |
| 82 | } else { |
| 83 | n_crc = 126; |
| 84 | } |
| 85 | |
| 86 | if (len < n_crc) |
| 87 | /* Not enough bytes available to get the CRC */ |
| 88 | return 0; |
| 89 | |
Arthur Heymans | 97b337b | 2018-01-22 01:26:53 +0100 | [diff] [blame] | 90 | return ddr3_crc16(spd, n_crc); |
Kyösti Mälkki | 7dc4b84 | 2016-11-18 18:41:17 +0200 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | /** |
| 94 | * \brief Calculate the CRC of a DDR3 SPD unique identifier |
| 95 | * |
| 96 | * @param spd pointer to raw SPD data |
| 97 | * @param len length of data in SPD |
| 98 | * |
| 99 | * @return the CRC of SPD data bytes 117..127, or 0 when spd data is truncated. |
| 100 | */ |
| 101 | u16 spd_ddr3_calc_unique_crc(u8 *spd, int len) |
| 102 | { |
| 103 | if (len < (117 + 11)) |
| 104 | /* Not enough bytes available to get the CRC */ |
| 105 | return 0; |
| 106 | |
Arthur Heymans | 97b337b | 2018-01-22 01:26:53 +0100 | [diff] [blame] | 107 | return ddr3_crc16(&spd[117], 11); |
Alexandru Gagniuc | 4c37e58 | 2013-12-17 13:08:01 -0500 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | /** |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 111 | * \brief Decode the raw SPD data |
| 112 | * |
| 113 | * Decodes a raw SPD data from a DDR3 DIMM, and organizes it into a |
| 114 | * @ref dimm_attr structure. The SPD data must first be read in a contiguous |
| 115 | * array, and passed to this function. |
| 116 | * |
Martin Roth | 63373ed | 2013-07-08 16:24:19 -0600 | [diff] [blame] | 117 | * @param dimm pointer to @ref dimm_attr structure where the decoded data is to |
Elyes HAOUAS | e3e3f4f | 2018-06-29 21:41:41 +0200 | [diff] [blame] | 118 | * be stored |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 119 | * @param spd array of raw data previously read from the SPD. |
| 120 | * |
| 121 | * @return @ref spd_status enumerator |
| 122 | * SPD_STATUS_OK -- decoding was successful |
| 123 | * SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD |
| 124 | * SPD_STATUS_CRC_ERROR -- CRC did not verify |
| 125 | * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was |
Elyes HAOUAS | e3e3f4f | 2018-06-29 21:41:41 +0200 | [diff] [blame] | 126 | * detected. |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 127 | */ |
| 128 | int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) |
| 129 | { |
Alexandru Gagniuc | 4c37e58 | 2013-12-17 13:08:01 -0500 | [diff] [blame] | 130 | int ret; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 131 | u16 crc, spd_crc; |
Nicola Corna | 76f8dbc | 2016-11-16 08:57:15 +0100 | [diff] [blame] | 132 | u8 capacity_shift, bus_width; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 133 | u8 reg8; |
| 134 | u32 mtb; /* medium time base */ |
Nicola Corna | 76f8dbc | 2016-11-16 08:57:15 +0100 | [diff] [blame] | 135 | u32 ftb; /* fine time base */ |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 136 | unsigned int val, param; |
| 137 | |
| 138 | ret = SPD_STATUS_OK; |
| 139 | |
| 140 | /* Don't assume we memset 0 dimm struct. Clear all our flags */ |
| 141 | dimm->flags.raw = 0; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 142 | dimm->dimms_per_channel = 3; |
| 143 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 144 | /* Make sure that the SPD dump is indeed from a DDR3 module */ |
| 145 | if (spd[2] != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
| 146 | printram("Not a DDR3 SPD!\n"); |
| 147 | dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; |
| 148 | return SPD_STATUS_INVALID; |
| 149 | } |
| 150 | dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3; |
Vladimir Serbinenko | 0e675f7 | 2014-12-07 13:56:48 +0100 | [diff] [blame] | 151 | dimm->dimm_type = spd[3] & 0xf; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 152 | |
Patrick Rudolph | 8c63935 | 2015-06-22 19:32:53 +0200 | [diff] [blame] | 153 | crc = spd_ddr3_calc_crc(spd, sizeof(spd_raw_data)); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 154 | /* Compare with the CRC in the SPD */ |
| 155 | spd_crc = (spd[127] << 8) + spd[126]; |
| 156 | /* Verify the CRC is correct */ |
| 157 | if (crc != spd_crc) { |
Patrick Rudolph | 78c6e3e | 2015-06-22 19:46:34 +0200 | [diff] [blame] | 158 | printram("ERROR: SPD CRC failed!!!\n"); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 159 | ret = SPD_STATUS_CRC_ERROR; |
| 160 | }; |
| 161 | |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 162 | printram(" Revision : %x\n", spd[1]); |
| 163 | printram(" Type : %x\n", spd[2]); |
| 164 | printram(" Key : %x\n", spd[3]); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 165 | |
| 166 | reg8 = spd[4]; |
| 167 | /* Number of memory banks */ |
| 168 | val = (reg8 >> 4) & 0x07; |
| 169 | if (val > 0x03) { |
| 170 | printram(" Invalid number of memory banks\n"); |
| 171 | ret = SPD_STATUS_INVALID_FIELD; |
| 172 | } |
| 173 | param = 1 << (val + 3); |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 174 | printram(" Banks : %u\n", param); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 175 | /* SDRAM capacity */ |
| 176 | capacity_shift = reg8 & 0x0f; |
| 177 | if (capacity_shift > 0x06) { |
| 178 | printram(" Invalid module capacity\n"); |
| 179 | ret = SPD_STATUS_INVALID_FIELD; |
| 180 | } |
| 181 | if (capacity_shift < 0x02) { |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 182 | printram(" Capacity : %u Mb\n", 256 << capacity_shift); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 183 | } else { |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 184 | printram(" Capacity : %u Gb\n", 1 << (capacity_shift - 2)); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | reg8 = spd[5]; |
| 188 | /* Row address bits */ |
| 189 | val = (reg8 >> 3) & 0x07; |
| 190 | if (val > 0x04) { |
| 191 | printram(" Invalid row address bits\n"); |
| 192 | ret = SPD_STATUS_INVALID_FIELD; |
| 193 | } |
| 194 | dimm->row_bits = val + 12; |
| 195 | /* Column address bits */ |
| 196 | val = reg8 & 0x07; |
| 197 | if (val > 0x03) { |
| 198 | printram(" Invalid column address bits\n"); |
| 199 | ret = SPD_STATUS_INVALID_FIELD; |
| 200 | } |
| 201 | dimm->col_bits = val + 9; |
| 202 | |
| 203 | /* Module nominal voltage */ |
| 204 | reg8 = spd[6]; |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 205 | printram(" Supported voltages :"); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 206 | if (reg8 & (1 << 2)) { |
| 207 | dimm->flags.operable_1_25V = 1; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 208 | dimm->voltage = 1250; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 209 | printram(" 1.25V"); |
| 210 | } |
| 211 | if (reg8 & (1 << 1)) { |
| 212 | dimm->flags.operable_1_35V = 1; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 213 | dimm->voltage = 1300; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 214 | printram(" 1.35V"); |
| 215 | } |
| 216 | if (!(reg8 & (1 << 0))) { |
| 217 | dimm->flags.operable_1_50V = 1; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 218 | dimm->voltage = 1500; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 219 | printram(" 1.5V"); |
| 220 | } |
| 221 | printram("\n"); |
| 222 | |
| 223 | /* Module organization */ |
| 224 | reg8 = spd[7]; |
| 225 | /* Number of ranks */ |
| 226 | val = (reg8 >> 3) & 0x07; |
| 227 | if (val > 3) { |
| 228 | printram(" Invalid number of ranks\n"); |
| 229 | ret = SPD_STATUS_INVALID_FIELD; |
| 230 | } |
| 231 | dimm->ranks = val + 1; |
| 232 | /* SDRAM device width */ |
| 233 | val = (reg8 & 0x07); |
| 234 | if (val > 3) { |
| 235 | printram(" Invalid SDRAM width\n"); |
| 236 | ret = SPD_STATUS_INVALID_FIELD; |
| 237 | } |
Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame] | 238 | dimm->width = (4 << val); |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 239 | printram(" SDRAM width : %u\n", dimm->width); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 240 | |
| 241 | /* Memory bus width */ |
| 242 | reg8 = spd[8]; |
| 243 | /* Bus extension */ |
| 244 | val = (reg8 >> 3) & 0x03; |
| 245 | if (val > 1) { |
| 246 | printram(" Invalid bus extension\n"); |
| 247 | ret = SPD_STATUS_INVALID_FIELD; |
| 248 | } |
| 249 | dimm->flags.is_ecc = val ? 1 : 0; |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 250 | printram(" Bus extension : %u bits\n", val ? 8 : 0); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 251 | /* Bus width */ |
| 252 | val = reg8 & 0x07; |
| 253 | if (val > 3) { |
| 254 | printram(" Invalid bus width\n"); |
| 255 | ret = SPD_STATUS_INVALID_FIELD; |
| 256 | } |
| 257 | bus_width = 8 << val; |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 258 | printram(" Bus width : %u\n", bus_width); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 259 | |
| 260 | /* We have all the info we need to compute the dimm size */ |
| 261 | /* Capacity is 256Mbit multiplied by the power of 2 specified in |
| 262 | * capacity_shift |
| 263 | * The rest is the JEDEC formula */ |
| 264 | dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width |
Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame] | 265 | * dimm->ranks) / dimm->width; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 266 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 267 | /* Medium Timebase = |
| 268 | * Medium Timebase (MTB) Dividend / |
| 269 | * Medium Timebase (MTB) Divisor */ |
| 270 | mtb = (((u32) spd[10]) << 8) / spd[11]; |
| 271 | |
| 272 | /* SDRAM Minimum Cycle Time (tCKmin) */ |
| 273 | dimm->tCK = spd[12] * mtb; |
| 274 | /* CAS Latencies Supported */ |
| 275 | dimm->cas_supported = (spd[15] << 8) + spd[14]; |
| 276 | /* Minimum CAS Latency Time (tAAmin) */ |
| 277 | dimm->tAA = spd[16] * mtb; |
| 278 | /* Minimum Write Recovery Time (tWRmin) */ |
| 279 | dimm->tWR = spd[17] * mtb; |
| 280 | /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ |
| 281 | dimm->tRCD = spd[18] * mtb; |
| 282 | /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ |
| 283 | dimm->tRRD = spd[19] * mtb; |
| 284 | /* Minimum Row Precharge Delay Time (tRPmin) */ |
| 285 | dimm->tRP = spd[20] * mtb; |
| 286 | /* Minimum Active to Precharge Delay Time (tRASmin) */ |
| 287 | dimm->tRAS = (((spd[21] & 0x0f) << 8) + spd[22]) * mtb; |
| 288 | /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ |
| 289 | dimm->tRC = (((spd[21] & 0xf0) << 4) + spd[23]) * mtb; |
| 290 | /* Minimum Refresh Recovery Delay Time (tRFCmin) */ |
| 291 | dimm->tRFC = ((spd[25] << 8) + spd[24]) * mtb; |
| 292 | /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ |
| 293 | dimm->tWTR = spd[26] * mtb; |
| 294 | /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ |
| 295 | dimm->tRTP = spd[27] * mtb; |
| 296 | /* Minimum Four Activate Window Delay Time (tFAWmin) */ |
| 297 | dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb; |
Dan Elkouby | 0c02420 | 2018-04-13 18:45:02 +0300 | [diff] [blame] | 298 | /* Minimum CAS Write Latency Time (tCWLmin) |
| 299 | * - not present in standard SPD */ |
| 300 | dimm->tCWL = 0; |
| 301 | /* System CMD Rate Mode - not present in standard SPD */ |
| 302 | dimm->tCMD = 0; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 303 | |
Nicola Corna | 76f8dbc | 2016-11-16 08:57:15 +0100 | [diff] [blame] | 304 | printram(" FTB timings :"); |
| 305 | /* FTB is introduced in SPD revision 1.1 */ |
| 306 | if (spd[1] >= 0x11 && spd[9] & 0x0f) { |
| 307 | printram(" yes\n"); |
| 308 | |
| 309 | /* Fine timebase (1/256 ps) = |
| 310 | * Fine Timebase (FTB) Dividend / |
| 311 | * Fine Timebase (FTB) Divisor */ |
| 312 | ftb = (((u16) spd[9] & 0xf0) << 4) / (spd[9] & 0x0f); |
| 313 | |
| 314 | /* SPD recommends to round up the MTB part and use a negative |
| 315 | * FTB, so a negative rounding should be always safe */ |
| 316 | |
| 317 | /* SDRAM Minimum Cycle Time (tCKmin) correction */ |
| 318 | dimm->tCK += (s32)((s8) spd[34] * ftb - 500) / 1000; |
| 319 | /* Minimum CAS Latency Time (tAAmin) correction */ |
| 320 | dimm->tAA += (s32)((s8) spd[35] * ftb - 500) / 1000; |
| 321 | /* Minimum RAS# to CAS# Delay Time (tRCDmin) correction */ |
| 322 | dimm->tRCD += (s32)((s8) spd[36] * ftb - 500) / 1000; |
| 323 | /* Minimum Row Precharge Delay Time (tRPmin) correction */ |
| 324 | dimm->tRP += (s32)((s8) spd[37] * ftb - 500) / 1000; |
| 325 | /* Minimum Active to Active/Refresh Delay Time (tRCmin) corr. */ |
| 326 | dimm->tRC += (s32)((s8) spd[38] * ftb - 500) / 1000; |
| 327 | } |
| 328 | else { |
| 329 | printram(" no\n"); |
| 330 | } |
| 331 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 332 | /* SDRAM Optional Features */ |
| 333 | reg8 = spd[30]; |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 334 | printram(" Optional features :"); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 335 | if (reg8 & 0x80) { |
| 336 | dimm->flags.dll_off_mode = 1; |
| 337 | printram(" DLL-Off_mode"); |
| 338 | } |
| 339 | if (reg8 & 0x02) { |
| 340 | dimm->flags.rzq7_supported = 1; |
| 341 | printram(" RZQ/7"); |
| 342 | } |
| 343 | if (reg8 & 0x01) { |
| 344 | dimm->flags.rzq6_supported = 1; |
| 345 | printram(" RZQ/6"); |
| 346 | } |
| 347 | printram("\n"); |
| 348 | |
| 349 | /* SDRAM Thermal and Refresh Options */ |
| 350 | reg8 = spd[31]; |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 351 | printram(" Thermal features :"); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 352 | if (reg8 & 0x80) { |
| 353 | dimm->flags.pasr = 1; |
| 354 | printram(" PASR"); |
| 355 | } |
| 356 | if (reg8 & 0x08) { |
| 357 | dimm->flags.odts = 1; |
| 358 | printram(" ODTS"); |
| 359 | } |
| 360 | if (reg8 & 0x04) { |
| 361 | dimm->flags.asr = 1; |
| 362 | printram(" ASR"); |
| 363 | } |
| 364 | if (reg8 & 0x02) { |
| 365 | dimm->flags.ext_temp_range = 1; |
| 366 | printram(" ext_temp_refresh"); |
| 367 | } |
| 368 | if (reg8 & 0x01) { |
| 369 | dimm->flags.ext_temp_refresh = 1; |
| 370 | printram(" ext_temp_range"); |
| 371 | } |
| 372 | printram("\n"); |
| 373 | |
| 374 | /* Module Thermal Sensor */ |
| 375 | reg8 = spd[32]; |
| 376 | if (reg8 & 0x80) |
| 377 | dimm->flags.therm_sensor = 1; |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 378 | printram(" Thermal sensor : %s\n", |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 379 | dimm->flags.therm_sensor ? "yes" : "no"); |
| 380 | |
| 381 | /* SDRAM Device Type */ |
| 382 | reg8 = spd[33]; |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 383 | printram(" Standard SDRAM : %s\n", (reg8 & 0x80) ? "no" : "yes"); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 384 | |
| 385 | if (spd[63] & 0x01) { |
| 386 | dimm->flags.pins_mirrored = 1; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 387 | } |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 388 | printram(" Rank1 Address bits : %s\n", |
| 389 | (spd[63] & 0x01) ? "mirrored" : "normal"); |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 390 | |
Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame] | 391 | dimm->reference_card = spd[62] & 0x1f; |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 392 | printram(" DIMM Reference card: %c\n", 'A' + dimm->reference_card); |
Vladimir Serbinenko | 7686a56 | 2014-05-18 11:05:56 +0200 | [diff] [blame] | 393 | |
Patrick Rudolph | 0769159 | 2016-02-29 18:21:00 +0100 | [diff] [blame] | 394 | dimm->manufacturer_id = (spd[118] << 8) | spd[117]; |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 395 | printram(" Manufacturer ID : %x\n", dimm->manufacturer_id); |
Patrick Rudolph | 0769159 | 2016-02-29 18:21:00 +0100 | [diff] [blame] | 396 | |
| 397 | dimm->part_number[16] = 0; |
| 398 | memcpy(dimm->part_number, &spd[128], 16); |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 399 | printram(" Part number : %s\n", dimm->part_number); |
Patrick Rudolph | 0769159 | 2016-02-29 18:21:00 +0100 | [diff] [blame] | 400 | |
Patrick Rudolph | 15e6469 | 2018-08-17 15:24:56 +0200 | [diff] [blame^] | 401 | memcpy(dimm->serial, &spd[SPD_DIMM_SERIAL_NUM], SPD_DIMM_SERIAL_LEN); |
| 402 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 403 | return ret; |
| 404 | } |
| 405 | |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 406 | /** |
| 407 | * \brief Decode the raw SPD XMP data |
| 408 | * |
| 409 | * Decodes a raw SPD XMP data from a DDR3 DIMM, and organizes it into a |
| 410 | * @ref dimm_attr structure. The SPD data must first be read in a contiguous |
| 411 | * array, and passed to this function. |
| 412 | * |
| 413 | * @param dimm pointer to @ref dimm_attr structure where the decoded data is to |
| 414 | * be stored |
| 415 | * @param spd array of raw data previously read from the SPD. |
| 416 | * |
| 417 | * @param profile select one of the profiles to load |
| 418 | * |
| 419 | * @return @ref spd_status enumerator |
| 420 | * SPD_STATUS_OK -- decoding was successful |
| 421 | * SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD |
| 422 | * SPD_STATUS_CRC_ERROR -- CRC did not verify |
| 423 | * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was |
| 424 | * detected. |
| 425 | */ |
| 426 | int spd_xmp_decode_ddr3(dimm_attr *dimm, |
| 427 | spd_raw_data spd, |
| 428 | enum ddr3_xmp_profile profile) |
| 429 | { |
| 430 | int ret; |
| 431 | u32 mtb; /* medium time base */ |
| 432 | u8 *xmp; /* pointer to XMP profile data */ |
| 433 | |
| 434 | /* need a valid SPD */ |
| 435 | ret = spd_decode_ddr3(dimm, spd); |
| 436 | if (ret != SPD_STATUS_OK) |
| 437 | return ret; |
| 438 | |
| 439 | /* search for magic header */ |
| 440 | if (spd[176] != 0x0C || spd[177] != 0x4A) { |
| 441 | printram("Not a DDR3 XMP profile!\n"); |
| 442 | dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; |
| 443 | return SPD_STATUS_INVALID; |
| 444 | } |
| 445 | |
| 446 | if (profile == DDR3_XMP_PROFILE_1) { |
| 447 | if (!(spd[178] & 1)) { |
| 448 | printram("Selected XMP profile disabled!\n"); |
| 449 | dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; |
| 450 | return SPD_STATUS_INVALID; |
| 451 | } |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 452 | |
| 453 | printram(" XMP Profile : 1\n"); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 454 | xmp = &spd[185]; |
| 455 | |
| 456 | /* Medium Timebase = |
| 457 | * Medium Timebase (MTB) Dividend / |
| 458 | * Medium Timebase (MTB) Divisor */ |
| 459 | mtb = (((u32) spd[180]) << 8) / spd[181]; |
| 460 | |
| 461 | dimm->dimms_per_channel = ((spd[178] >> 2) & 0x3) + 1; |
| 462 | } else { |
| 463 | if (!(spd[178] & 2)) { |
| 464 | printram("Selected XMP profile disabled!\n"); |
| 465 | dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; |
| 466 | return SPD_STATUS_INVALID; |
| 467 | } |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 468 | printram(" XMP Profile : 2\n"); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 469 | xmp = &spd[220]; |
| 470 | |
| 471 | /* Medium Timebase = |
| 472 | * Medium Timebase (MTB) Dividend / |
| 473 | * Medium Timebase (MTB) Divisor */ |
| 474 | mtb = (((u32) spd[182]) << 8) / spd[183]; |
| 475 | |
| 476 | dimm->dimms_per_channel = ((spd[178] >> 4) & 0x3) + 1; |
| 477 | } |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 478 | |
| 479 | printram(" Max DIMMs/channel : %u\n", |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 480 | dimm->dimms_per_channel); |
| 481 | |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 482 | printram(" XMP Revision : %u.%u\n", spd[179] >> 4, spd[179] & 0xf); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 483 | |
| 484 | /* calculate voltage in mV */ |
| 485 | dimm->voltage = (xmp[0] & 1) * 50; |
| 486 | dimm->voltage += ((xmp[0] >> 1) & 0xf) * 100; |
| 487 | dimm->voltage += ((xmp[0] >> 5) & 0x3) * 1000; |
Patrick Rudolph | 66a98ee | 2016-03-13 13:02:16 +0100 | [diff] [blame] | 488 | |
| 489 | printram(" Requested voltage : %u mV\n", dimm->voltage); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 490 | |
| 491 | /* SDRAM Minimum Cycle Time (tCKmin) */ |
| 492 | dimm->tCK = xmp[1] * mtb; |
| 493 | /* CAS Latencies Supported */ |
Dan Elkouby | 0c02420 | 2018-04-13 18:45:02 +0300 | [diff] [blame] | 494 | dimm->cas_supported = ((xmp[4] << 8) + xmp[3]) & 0x7fff; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 495 | /* Minimum CAS Latency Time (tAAmin) */ |
| 496 | dimm->tAA = xmp[2] * mtb; |
| 497 | /* Minimum Write Recovery Time (tWRmin) */ |
| 498 | dimm->tWR = xmp[8] * mtb; |
| 499 | /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ |
| 500 | dimm->tRCD = xmp[7] * mtb; |
| 501 | /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ |
| 502 | dimm->tRRD = xmp[17] * mtb; |
| 503 | /* Minimum Row Precharge Delay Time (tRPmin) */ |
| 504 | dimm->tRP = xmp[6] * mtb; |
| 505 | /* Minimum Active to Precharge Delay Time (tRASmin) */ |
| 506 | dimm->tRAS = (((xmp[9] & 0x0f) << 8) + xmp[10]) * mtb; |
| 507 | /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ |
| 508 | dimm->tRC = (((xmp[9] & 0xf0) << 4) + xmp[11]) * mtb; |
| 509 | /* Minimum Refresh Recovery Delay Time (tRFCmin) */ |
| 510 | dimm->tRFC = ((xmp[15] << 8) + xmp[14]) * mtb; |
| 511 | /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ |
| 512 | dimm->tWTR = xmp[20] * mtb; |
| 513 | /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ |
| 514 | dimm->tRTP = xmp[16] * mtb; |
| 515 | /* Minimum Four Activate Window Delay Time (tFAWmin) */ |
| 516 | dimm->tFAW = (((xmp[18] & 0x0f) << 8) + xmp[19]) * mtb; |
Dan Elkouby | 0c02420 | 2018-04-13 18:45:02 +0300 | [diff] [blame] | 517 | /* Minimum CAS Write Latency Time (tCWLmin) */ |
| 518 | dimm->tCWL = xmp[5] * mtb; |
| 519 | /* System CMD Rate Mode */ |
| 520 | dimm->tCMD = xmp[23] * mtb; |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 521 | |
| 522 | return ret; |
| 523 | } |
| 524 | |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 525 | /* |
| 526 | * The information printed below has a more informational character, and is not |
| 527 | * necessarily tied in to RAM init debugging. Hence, we stop using printram(), |
| 528 | * and use the standard printk()'s below. |
| 529 | */ |
| 530 | |
| 531 | static void print_ns(const char *msg, u32 val) |
| 532 | { |
| 533 | u32 mant, fp; |
| 534 | mant = val / 256; |
| 535 | fp = (val % 256) * 1000 / 256; |
| 536 | |
| 537 | printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp); |
| 538 | } |
| 539 | |
| 540 | /** |
| 541 | * \brief Print the info in DIMM |
| 542 | * |
| 543 | * Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is |
| 544 | * selected, or for a purely informative output. |
| 545 | * |
Martin Roth | 63373ed | 2013-07-08 16:24:19 -0600 | [diff] [blame] | 546 | * @param dimm pointer to already decoded @ref dimm_attr structure |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 547 | */ |
| 548 | void dram_print_spd_ddr3(const dimm_attr * dimm) |
| 549 | { |
| 550 | u16 val16; |
| 551 | int i; |
| 552 | |
| 553 | printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); |
| 554 | printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); |
| 555 | printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); |
| 556 | printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); |
| 557 | |
| 558 | /* CAS Latencies Supported */ |
| 559 | val16 = dimm->cas_supported; |
| 560 | printk(BIOS_INFO, " CAS latencies :"); |
| 561 | i = 0; |
| 562 | do { |
| 563 | if (val16 & 1) |
| 564 | printk(BIOS_INFO, " %u", i + 4); |
| 565 | i++; |
| 566 | val16 >>= 1; |
| 567 | } while (val16); |
| 568 | printk(BIOS_INFO, "\n"); |
| 569 | |
| 570 | print_ns(" tCKmin : ", dimm->tCK); |
| 571 | print_ns(" tAAmin : ", dimm->tAA); |
| 572 | print_ns(" tWRmin : ", dimm->tWR); |
| 573 | print_ns(" tRCDmin : ", dimm->tRCD); |
| 574 | print_ns(" tRRDmin : ", dimm->tRRD); |
| 575 | print_ns(" tRPmin : ", dimm->tRP); |
| 576 | print_ns(" tRASmin : ", dimm->tRAS); |
| 577 | print_ns(" tRCmin : ", dimm->tRC); |
| 578 | print_ns(" tRFCmin : ", dimm->tRFC); |
| 579 | print_ns(" tWTRmin : ", dimm->tWTR); |
| 580 | print_ns(" tRTPmin : ", dimm->tRTP); |
| 581 | print_ns(" tFAWmin : ", dimm->tFAW); |
Dan Elkouby | 0c02420 | 2018-04-13 18:45:02 +0300 | [diff] [blame] | 582 | /* Those values are only relevant if an XMP profile sets them */ |
| 583 | if (dimm->tCWL) |
| 584 | print_ns(" tCWLmin : ", dimm->tCWL); |
| 585 | if (dimm->tCMD) |
| 586 | printk(BIOS_INFO, " tCMDmin : %3u\n", |
| 587 | DIV_ROUND_UP(dimm->tCMD, 256)); |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 588 | } |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 589 | |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 590 | /*============================================================================== |
| 591 | *= DDR3 MRS helpers |
| 592 | *----------------------------------------------------------------------------*/ |
| 593 | |
| 594 | /* |
| 595 | * MRS command structure: |
| 596 | * cmd[15:0] = Address pins MA[15:0] |
| 597 | * cmd[18:16] = Bank address BA[2:0] |
| 598 | */ |
| 599 | |
| 600 | /* Map tWR value to a bitmask of the MR0 cycle */ |
| 601 | static u16 ddr3_twr_to_mr0_map(u8 twr) |
| 602 | { |
| 603 | if ((twr >= 5) && (twr <= 8)) |
| 604 | return (twr - 4) << 9; |
| 605 | |
| 606 | /* |
| 607 | * From 8T onwards, we can only use even values. Round up if we are |
| 608 | * given an odd value. |
| 609 | */ |
| 610 | if ((twr >= 9) && (twr <= 14)) |
| 611 | return ((twr + 1) >> 1) << 9; |
| 612 | |
| 613 | /* tWR == 16T is [000] */ |
| 614 | return 0; |
| 615 | } |
| 616 | |
| 617 | /* Map the CAS latency to a bitmask for the MR0 cycle */ |
| 618 | static u16 ddr3_cas_to_mr0_map(u8 cas) |
| 619 | { |
| 620 | u16 mask = 0; |
| 621 | /* A[6:4] are bits [2:0] of (CAS - 4) */ |
| 622 | mask = ((cas - 4) & 0x07) << 4; |
| 623 | |
| 624 | /* A2 is the MSB of (CAS - 4) */ |
| 625 | if ((cas - 4) & (1 << 3)) |
| 626 | mask |= (1 << 2); |
| 627 | |
| 628 | return mask; |
| 629 | } |
| 630 | |
| 631 | /** |
| 632 | * \brief Get command address for a DDR3 MR0 command |
| 633 | * |
| 634 | * The DDR3 specification only covers odd write_recovery up to 7T. If an odd |
| 635 | * write_recovery greater than 7 is specified, it will be rounded up. If a tWR |
| 636 | * greater than 8 is specified, it is recommended to explicitly round it up or |
| 637 | * down before calling this function. |
| 638 | * |
| 639 | * write_recovery and cas are given in clock cycles. For example, a CAS of 7T |
| 640 | * should be given as 7. |
| 641 | * |
Martin Roth | 98b698c | 2015-01-06 21:02:52 -0700 | [diff] [blame] | 642 | * @param precharge_pd |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 643 | * @param write_recovery Write recovery latency, tWR in clock cycles. |
Martin Roth | 98b698c | 2015-01-06 21:02:52 -0700 | [diff] [blame] | 644 | * @param dll_reset |
| 645 | * @param mode |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 646 | * @param cas CAS latency in clock cycles. |
Martin Roth | 98b698c | 2015-01-06 21:02:52 -0700 | [diff] [blame] | 647 | * @param burst_type |
| 648 | * @param burst_length |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 649 | */ |
| 650 | mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, |
| 651 | u8 write_recovery, |
| 652 | enum ddr3_mr0_dll_reset dll_reset, |
| 653 | enum ddr3_mr0_mode mode, |
| 654 | u8 cas, |
| 655 | enum ddr3_mr0_burst_type burst_type, |
| 656 | enum ddr3_mr0_burst_length burst_length) |
| 657 | { |
| 658 | mrs_cmd_t cmd = 0 << 16; |
| 659 | |
| 660 | if (precharge_pd == DDR3_MR0_PRECHARGE_FAST) |
| 661 | cmd |= (1 << 12); |
| 662 | |
| 663 | cmd |= ddr3_twr_to_mr0_map(write_recovery); |
| 664 | |
| 665 | if (dll_reset == DDR3_MR0_DLL_RESET_YES) |
| 666 | cmd |= (1 << 8); |
| 667 | |
| 668 | if (mode == DDR3_MR0_MODE_TEST) |
| 669 | cmd |= (1 << 7); |
| 670 | |
| 671 | cmd |= ddr3_cas_to_mr0_map(cas); |
| 672 | |
| 673 | if (burst_type == DDR3_MR0_BURST_TYPE_INTERLEAVED) |
| 674 | cmd |= (1 << 3); |
| 675 | |
| 676 | cmd |= (burst_length & 0x03) << 0; |
| 677 | |
| 678 | return cmd; |
| 679 | } |
| 680 | |
| 681 | static u16 ddr3_rtt_nom_to_mr1_map(enum ddr3_mr1_rtt_nom rtt_nom) |
| 682 | { |
| 683 | u16 mask = 0; |
| 684 | /* A9 <-> rtt_nom[2] */ |
| 685 | if (rtt_nom & (1 << 2)) |
| 686 | mask |= (1 << 9); |
| 687 | /* A6 <-> rtt_nom[1] */ |
| 688 | if (rtt_nom & (1 << 1)) |
| 689 | mask |= (1 << 6); |
| 690 | /* A2 <-> rtt_nom[0] */ |
| 691 | if (rtt_nom & (1 << 0)) |
| 692 | mask |= (1 << 2); |
| 693 | |
| 694 | return mask; |
| 695 | } |
| 696 | |
| 697 | static u16 ddr3_ods_to_mr1_map(enum ddr3_mr1_ods ods) |
| 698 | { |
| 699 | u16 mask = 0; |
| 700 | /* A5 <-> ods[1] */ |
| 701 | if (ods & (1 << 1)) |
| 702 | mask |= (1 << 5); |
| 703 | /* A1 <-> ods[0] */ |
| 704 | if (ods & (1 << 0)) |
| 705 | mask |= (1 << 1); |
| 706 | |
| 707 | return mask; |
| 708 | } |
| 709 | |
| 710 | /** |
| 711 | * \brief Get command address for a DDR3 MR1 command |
| 712 | */ |
| 713 | mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, |
| 714 | enum ddr3_mr1_tqds tqds, |
| 715 | enum ddr3_mr1_rtt_nom rtt_nom, |
| 716 | enum ddr3_mr1_write_leveling write_leveling, |
| 717 | enum ddr3_mr1_ods ods, |
| 718 | enum ddr3_mr1_additive_latency additive_latency, |
| 719 | enum ddr3_mr1_dll dll_disable) |
| 720 | { |
| 721 | mrs_cmd_t cmd = 1 << 16; |
| 722 | |
| 723 | if (qoff == DDR3_MR1_QOFF_DISABLE) |
| 724 | cmd |= (1 << 12); |
| 725 | |
| 726 | if (tqds == DDR3_MR1_TQDS_ENABLE) |
| 727 | cmd |= (1 << 11); |
| 728 | |
| 729 | cmd |= ddr3_rtt_nom_to_mr1_map(rtt_nom); |
| 730 | |
| 731 | if (write_leveling == DDR3_MR1_WRLVL_ENABLE) |
| 732 | cmd |= (1 << 7); |
| 733 | |
| 734 | cmd |= ddr3_ods_to_mr1_map(ods); |
| 735 | |
| 736 | cmd |= (additive_latency & 0x03) << 3; |
| 737 | |
| 738 | if (dll_disable == DDR3_MR1_DLL_DISABLE) |
| 739 | cmd |= (1 << 0); |
| 740 | |
| 741 | return cmd; |
| 742 | } |
| 743 | |
| 744 | /** |
| 745 | * \brief Get command address for a DDR3 MR2 command |
| 746 | * |
| 747 | * cas_cwl is given in clock cycles. For example, a cas_cwl of 7T should be |
| 748 | * given as 7. |
| 749 | * |
Martin Roth | 98b698c | 2015-01-06 21:02:52 -0700 | [diff] [blame] | 750 | * @param rtt_wr |
| 751 | * @param extended_temp |
| 752 | * @param self_refresh |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 753 | * @param cas_cwl CAS write latency in clock cycles. |
| 754 | */ |
Martin Roth | 98b698c | 2015-01-06 21:02:52 -0700 | [diff] [blame] | 755 | |
Alexandru Gagniuc | 78706fd | 2013-06-03 13:58:10 -0500 | [diff] [blame] | 756 | mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, |
| 757 | enum ddr3_mr2_srt_range extended_temp, |
| 758 | enum ddr3_mr2_asr self_refresh, u8 cas_cwl) |
| 759 | { |
| 760 | mrs_cmd_t cmd = 2 << 16; |
| 761 | |
| 762 | cmd |= (rtt_wr & 0x03) << 9; |
| 763 | |
| 764 | if (extended_temp == DDR3_MR2_SRT_EXTENDED) |
| 765 | cmd |= (1 << 7); |
| 766 | |
| 767 | if (self_refresh == DDR3_MR2_ASR_AUTO) |
| 768 | cmd |= (1 << 6); |
| 769 | |
| 770 | cmd |= ((cas_cwl - 5) & 0x07) << 3; |
| 771 | |
| 772 | return cmd; |
| 773 | } |
| 774 | |
| 775 | /** |
| 776 | * \brief Get command address for a DDR3 MR3 command |
| 777 | * |
| 778 | * @param dataflow_from_mpr Specify a non-zero value to put DRAM in read |
| 779 | * leveling mode. Zero for normal operation. |
| 780 | */ |
| 781 | mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr) |
| 782 | { |
| 783 | mrs_cmd_t cmd = 3 << 16; |
| 784 | |
| 785 | if (dataflow_from_mpr) |
| 786 | cmd |= (1 << 2); |
| 787 | |
| 788 | return cmd; |
| 789 | } |
| 790 | |
| 791 | /** |
| 792 | * \brief Mirror the address bits for this MRS command |
| 793 | * |
| 794 | * Swap the following bits in the MRS command: |
| 795 | * - MA3 <-> MA4 |
| 796 | * - MA5 <-> MA6 |
| 797 | * - MA7 <-> MA8 |
| 798 | * - BA0 <-> BA1 |
| 799 | */ |
| 800 | mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd) |
| 801 | { |
| 802 | u32 downshift, upshift; |
| 803 | /* High bits= A4 | A6 | A8 | BA1 */ |
| 804 | /* Low bits = A3 | A5 | A7 | BA0 */ |
| 805 | u32 lowbits = (1 << 3) | (1 << 5) | (1 << 7) | (1 << 16); |
| 806 | downshift = (cmd & (lowbits << 1)); |
| 807 | upshift = (cmd & lowbits); |
| 808 | cmd &= ~(lowbits | (lowbits << 1)); |
| 809 | cmd |= (downshift >> 1) | (upshift << 1); |
| 810 | return cmd; |
Alexandru Gagniuc | f97ff3f | 2013-05-21 14:43:45 -0500 | [diff] [blame] | 811 | } |