Joey Peng | 64be788 | 2021-08-03 15:35:05 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
Joey Peng | cd1006c | 2023-06-17 09:30:04 +0800 | [diff] [blame] | 5 | #include <console/console.h> |
Joey Peng | 64be788 | 2021-08-03 15:35:05 +0800 | [diff] [blame] | 6 | #include <gpio.h> |
Joey Peng | cd1006c | 2023-06-17 09:30:04 +0800 | [diff] [blame] | 7 | #include <memory_info.h> |
| 8 | #include <string.h> |
Joey Peng | 64be788 | 2021-08-03 15:35:05 +0800 | [diff] [blame] | 9 | |
| 10 | static const struct mb_cfg baseboard_memcfg = { |
| 11 | .type = MEM_TYPE_LP4X, |
| 12 | |
| 13 | .rcomp = { |
| 14 | /* Baseboard uses only 100ohm Rcomp resistors */ |
| 15 | .resistor = 100, |
| 16 | |
| 17 | /* Baseboard Rcomp target values */ |
| 18 | .targets = {40, 30, 30, 30, 30}, |
| 19 | }, |
| 20 | |
| 21 | /* DQ byte map */ |
| 22 | .lpx_dq_map = { |
| 23 | .ddr0 = { |
| 24 | .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, |
| 25 | .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, |
| 26 | }, |
| 27 | .ddr1 = { |
| 28 | .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, |
| 29 | .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, |
| 30 | }, |
| 31 | .ddr2 = { |
| 32 | .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, |
| 33 | .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, |
| 34 | }, |
| 35 | .ddr3 = { |
| 36 | .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, |
| 37 | .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, |
| 38 | }, |
| 39 | .ddr4 = { |
| 40 | .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, |
| 41 | .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, |
| 42 | }, |
| 43 | .ddr5 = { |
| 44 | .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, |
| 45 | .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, |
| 46 | }, |
| 47 | .ddr6 = { |
| 48 | .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, |
| 49 | .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, |
| 50 | }, |
| 51 | .ddr7 = { |
| 52 | .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, |
| 53 | .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, |
| 54 | }, |
| 55 | }, |
| 56 | |
| 57 | /* DQS CPU<>DRAM map */ |
| 58 | .lpx_dqs_map = { |
| 59 | .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, |
| 60 | .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, |
| 61 | .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, |
| 62 | .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, |
| 63 | .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, |
| 64 | .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, |
| 65 | .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, |
| 66 | .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, |
| 67 | }, |
| 68 | |
| 69 | .ect = 1, /* Enable Early Command Training */ |
| 70 | }; |
| 71 | |
Joey Peng | cd1006c | 2023-06-17 09:30:04 +0800 | [diff] [blame] | 72 | static const struct mb_cfg hynix_memconfig = { |
| 73 | .type = MEM_TYPE_LP4X, |
| 74 | |
| 75 | .rcomp = { |
| 76 | /* Baseboard uses only 100ohm Rcomp resistors */ |
| 77 | .resistor = 100, |
| 78 | |
| 79 | /* Baseboard Rcomp target values */ |
| 80 | .targets = {40, 30, 30, 30, 30}, |
| 81 | }, |
| 82 | |
| 83 | /* DQ byte map */ |
| 84 | .lpx_dq_map = { |
| 85 | .ddr0 = { |
| 86 | .dq0 = { 9, 11, 8, 10, 12, 14, 13, 15, }, |
| 87 | .dq1 = { 4, 7, 6, 5, 2, 3, 0, 1, }, |
| 88 | }, |
| 89 | .ddr1 = { |
| 90 | .dq0 = { 15, 12, 14, 13, 9, 10, 11, 8, }, |
| 91 | .dq1 = { 0, 1, 3, 2, 7, 5, 4, 6, }, |
| 92 | }, |
| 93 | .ddr2 = { |
| 94 | .dq0 = { 2, 3, 1, 0, 6, 7, 5, 4, }, |
| 95 | .dq1 = { 15, 9, 14, 8, 11, 10, 13, 12, }, |
| 96 | }, |
| 97 | .ddr3 = { |
| 98 | .dq0 = { 3, 1, 2, 0, 4, 6, 7, 5, }, |
| 99 | .dq1 = { 13, 15, 14, 12, 11, 9, 8, 10, }, |
| 100 | }, |
| 101 | .ddr4 = { |
| 102 | .dq0 = { 13, 12, 14, 15, 9, 8, 10, 11, }, |
| 103 | .dq1 = { 4, 7, 5, 6, 1, 2, 0, 3, }, |
| 104 | }, |
| 105 | .ddr5 = { |
| 106 | .dq0 = { 5, 0, 6, 4, 3, 1, 7, 2, }, |
| 107 | .dq1 = { 11, 9, 10, 8, 15, 12, 14, 13, }, |
| 108 | }, |
| 109 | .ddr6 = { |
| 110 | .dq0 = { 15, 12, 14, 13, 10, 9, 11, 8, }, |
| 111 | .dq1 = { 0, 1, 2, 3, 5, 6, 4, 7, }, |
| 112 | }, |
| 113 | .ddr7 = { |
| 114 | .dq0 = { 0, 3, 1, 2, 4, 5, 6, 7, }, |
| 115 | .dq1 = { 11, 8, 13, 14, 9, 12, 15, 10, }, |
| 116 | }, |
| 117 | }, |
| 118 | |
| 119 | /* DQS CPU<>DRAM map */ |
| 120 | .lpx_dqs_map = { |
| 121 | .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, |
| 122 | .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, |
| 123 | .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, |
| 124 | .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, |
| 125 | .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, |
| 126 | .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, |
| 127 | .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, |
| 128 | .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, |
| 129 | }, |
| 130 | |
| 131 | .ect = 1, /* Enable Early Command Training */ |
| 132 | |
| 133 | .cs_pi_start_high_in_ect = 1, |
| 134 | }; |
Tim Wawrzynczak | c48ec7b | 2022-03-28 13:25:16 -0600 | [diff] [blame] | 135 | const struct mb_cfg *variant_memory_params(void) |
Joey Peng | 64be788 | 2021-08-03 15:35:05 +0800 | [diff] [blame] | 136 | { |
Joey Peng | cd1006c | 2023-06-17 09:30:04 +0800 | [diff] [blame] | 137 | const char *dram_part_num = mainboard_get_dram_part_num(); |
Wisley Chen | 15cb0d5 | 2023-09-05 13:12:10 +0800 | [diff] [blame^] | 138 | if (dram_part_num) { |
| 139 | if (strcmp(dram_part_num, "H54G46CYRBX267N") == 0) { |
| 140 | printk(BIOS_INFO, "Enable cs_pi_start_high_in_ect for Hynix DRAM part\n"); |
| 141 | return &hynix_memconfig; |
| 142 | } |
Joey Peng | cd1006c | 2023-06-17 09:30:04 +0800 | [diff] [blame] | 143 | } |
Wisley Chen | 15cb0d5 | 2023-09-05 13:12:10 +0800 | [diff] [blame^] | 144 | return &baseboard_memcfg; |
Joey Peng | 64be788 | 2021-08-03 15:35:05 +0800 | [diff] [blame] | 145 | } |
| 146 | |
Tim Wawrzynczak | c48ec7b | 2022-03-28 13:25:16 -0600 | [diff] [blame] | 147 | int variant_memory_sku(void) |
Joey Peng | 64be788 | 2021-08-03 15:35:05 +0800 | [diff] [blame] | 148 | { |
| 149 | /* |
| 150 | * Memory configuration board straps |
| 151 | * GPIO_MEM_CONFIG_0 GPP_E11 |
| 152 | * GPIO_MEM_CONFIG_1 GPP_E2 |
| 153 | * GPIO_MEM_CONFIG_2 GPP_E1 |
| 154 | * GPIO_MEM_CONFIG_3 GPP_E12 |
| 155 | */ |
| 156 | gpio_t spd_gpios[] = { |
| 157 | GPP_E11, |
| 158 | GPP_E2, |
| 159 | GPP_E1, |
| 160 | GPP_E12, |
| 161 | }; |
| 162 | |
| 163 | return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); |
| 164 | } |
| 165 | |
Tim Wawrzynczak | c48ec7b | 2022-03-28 13:25:16 -0600 | [diff] [blame] | 166 | bool variant_is_half_populated(void) |
Joey Peng | 64be788 | 2021-08-03 15:35:05 +0800 | [diff] [blame] | 167 | { |
| 168 | /* GPIO_MEM_CH_SEL GPP_E13 */ |
| 169 | return gpio_get(GPP_E13); |
| 170 | } |