Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Chromium OS Authors |
| 5 | * Copyright (C) 2013 Vladimir Serbinenko |
| 6 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <arch/io.h> |
| 19 | #include <console/console.h> |
| 20 | #include <delay.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <string.h> |
| 25 | #include <device/pci_ops.h> |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 26 | #include <commonlib/helpers.h> |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 27 | #include <cbmem.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 28 | |
| 29 | #include "drivers/intel/gma/i915_reg.h" |
| 30 | #include "chip.h" |
| 31 | #include "x4x.h" |
| 32 | #include <drivers/intel/gma/intel_bios.h> |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 33 | #include <drivers/intel/gma/edid.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 34 | #include <drivers/intel/gma/i915.h> |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 35 | #include <drivers/intel/gma/opregion.h> |
Nico Huber | f2dd049 | 2017-10-29 15:42:44 +0100 | [diff] [blame] | 36 | #include <drivers/intel/gma/libgfxinit.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 37 | #include <pc80/vga.h> |
| 38 | #include <pc80/vga_io.h> |
| 39 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 40 | #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX) |
| 41 | #include <southbridge/intel/i82801jx/nvs.h> |
| 42 | #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) |
| 43 | #include <southbridge/intel/i82801gx/nvs.h> |
| 44 | #endif |
| 45 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 46 | #define BASE_FREQUENCY 96000 |
| 47 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 48 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 49 | { |
| 50 | const global_nvs_t *gnvs_ptr = gnvs; |
| 51 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 52 | } |
| 53 | |
| 54 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 55 | { |
| 56 | global_nvs_t *gnvs_ptr = gnvs; |
| 57 | if (gnvs_ptr) |
| 58 | gnvs_ptr->aslb = aslb; |
| 59 | } |
| 60 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 61 | static void gma_func0_init(struct device *dev) |
| 62 | { |
| 63 | u32 reg32; |
| 64 | |
| 65 | /* IGD needs to be Bus Master */ |
| 66 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 67 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 68 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 69 | |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 70 | /* configure GMBUSFREQ */ |
Nico Huber | 15b83da | 2019-01-12 15:05:20 +0100 | [diff] [blame^] | 71 | pci_update_config16(dev, 0xcc, ~0x1ff, 0xbc); |
Arthur Heymans | de14ea7 | 2016-09-04 16:01:11 +0200 | [diff] [blame] | 72 | |
Stefan Tauner | 3e3bae0 | 2018-09-03 19:02:13 +0200 | [diff] [blame] | 73 | int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 74 | |
Arthur Heymans | e809305 | 2018-06-07 19:19:42 +0200 | [diff] [blame] | 75 | if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 76 | if (vga_disable) { |
| 77 | printk(BIOS_INFO, |
| 78 | "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); |
| 79 | } else { |
| 80 | int lightup_ok; |
| 81 | gma_gfxinit(&lightup_ok); |
| 82 | } |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 83 | } else { |
Damien Zammit | 216fc50 | 2016-01-22 19:13:18 +1100 | [diff] [blame] | 84 | pci_dev_init(dev); |
Arthur Heymans | 2e7efe6 | 2017-05-06 18:05:57 +0200 | [diff] [blame] | 85 | } |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 86 | |
| 87 | intel_gma_restore_opregion(); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 88 | } |
| 89 | |
Arthur Heymans | c80748c | 2017-02-26 23:04:51 +0100 | [diff] [blame] | 90 | static void gma_func0_disable(struct device *dev) |
| 91 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 92 | struct device *dev_host = pcidev_on_root(0, 0); |
Arthur Heymans | c80748c | 2017-02-26 23:04:51 +0100 | [diff] [blame] | 93 | u16 ggc; |
| 94 | |
| 95 | ggc = pci_read_config16(dev_host, D0F0_GGC); |
| 96 | ggc |= (1 << 1); /* VGA cycles to discrete GPU */ |
| 97 | pci_write_config16(dev_host, D0F0_GGC, ggc); |
| 98 | } |
| 99 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 100 | static void gma_set_subsystem(struct device *dev, unsigned int vendor, |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 101 | unsigned int device) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 102 | { |
| 103 | if (!vendor || !device) { |
| 104 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 105 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 106 | } else { |
| 107 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 108 | ((device & 0xffff) << 16) | (vendor & |
| 109 | 0xffff)); |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | const struct i915_gpu_controller_info * |
| 114 | intel_gma_get_controller_info(void) |
| 115 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 116 | struct device *dev = pcidev_on_root(0x2, 0); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 117 | if (!dev) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 118 | return NULL; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 119 | struct northbridge_intel_x4x_config *chip = dev->chip_info; |
| 120 | return &chip->gfx; |
| 121 | } |
| 122 | |
Elyes HAOUAS | fea02e1 | 2018-02-08 14:59:03 +0100 | [diff] [blame] | 123 | static void gma_ssdt(struct device *device) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 124 | { |
| 125 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 126 | if (!gfx) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 127 | return; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 128 | |
| 129 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 130 | } |
| 131 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 132 | static unsigned long |
| 133 | gma_write_acpi_tables(struct device *const dev, |
| 134 | unsigned long current, |
| 135 | struct acpi_rsdp *const rsdp) |
| 136 | { |
| 137 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
| 138 | global_nvs_t *gnvs; |
| 139 | |
| 140 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
| 141 | return current; |
| 142 | |
| 143 | current += sizeof(igd_opregion_t); |
| 144 | |
| 145 | /* GNVS has been already set up */ |
| 146 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 147 | if (gnvs) { |
| 148 | /* IGD OpRegion Base Address */ |
| 149 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
| 150 | } else { |
| 151 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
| 152 | } |
| 153 | |
| 154 | current = acpi_align_current(current); |
| 155 | return current; |
| 156 | } |
| 157 | |
| 158 | static const char *gma_acpi_name(const struct device *dev) |
| 159 | { |
| 160 | return "GFX0"; |
| 161 | } |
| 162 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 163 | static struct pci_operations gma_pci_ops = { |
| 164 | .set_subsystem = gma_set_subsystem, |
| 165 | }; |
| 166 | |
| 167 | static struct device_operations gma_func0_ops = { |
| 168 | .read_resources = pci_dev_read_resources, |
| 169 | .set_resources = pci_dev_set_resources, |
| 170 | .enable_resources = pci_dev_enable_resources, |
| 171 | .acpi_fill_ssdt_generator = gma_ssdt, |
| 172 | .init = gma_func0_init, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 173 | .ops_pci = &gma_pci_ops, |
Arthur Heymans | c80748c | 2017-02-26 23:04:51 +0100 | [diff] [blame] | 174 | .disable = gma_func0_disable, |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 175 | .acpi_name = gma_acpi_name, |
| 176 | .write_acpi_tables = gma_write_acpi_tables, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 177 | }; |
| 178 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 179 | static const unsigned short pci_device_ids[] = { |
Arthur Heymans | 9e70ce0 | 2016-12-16 15:32:32 +0100 | [diff] [blame] | 180 | 0x2e02, /* Eaglelake */ |
| 181 | 0x2e12, /* Q43/Q45 */ |
| 182 | 0x2e22, /* G43/G45 */ |
| 183 | 0x2e32, /* G41 */ |
| 184 | 0x2e42, /* B43 */ |
| 185 | 0x2e92, /* B43_I */ |
| 186 | 0 |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 187 | }; |
| 188 | |
| 189 | static const struct pci_driver gma __pci_driver = { |
| 190 | .ops = &gma_func0_ops, |
| 191 | .vendor = PCI_VENDOR_ID_INTEL, |
| 192 | .devices = pci_device_ids, |
| 193 | }; |