V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <device/pci_ids.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <soc/ramstage.h> |
| 7 | #include <soc/vr_config.h> |
| 8 | #include <console/console.h> |
| 9 | #include <intelblocks/cpulib.h> |
| 10 | |
| 11 | /* |
| 12 | * VR Configurations for IA and GT domains for ADL-P SKU's. |
Curtis Chen | 0c54461 | 2021-11-19 11:38:12 +0800 | [diff] [blame] | 13 | * Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation |
| 14 | * for ADL-P 482(28W) and 442(45W). |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 15 | * |
| 16 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 17 | * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | |
| 18 | * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | |
| 19 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 20 | * | ADL-P 682(45W) | IA | 2.3 | 2.3 | 160 | 57 | 28000 | |
| 21 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 22 | * | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | |
| 23 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
Curtis Chen | 0c54461 | 2021-11-19 11:38:12 +0800 | [diff] [blame] | 24 | * | ADL-P 482(28W) | IA | 2.3 | 2.3 | 85 | 40 | 28000 | |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 25 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 26 | * | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | |
| 27 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 28 | * | ADL-P 282(15W) | IA | 2.8 | 2.8 | 80 | 20 | 28000 | |
| 29 | * + +-----------+-------+-------+---------+-------------+----------+ |
| 30 | * | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | |
| 31 | * +----------------+-----------+-------+-------+---------+-------------+----------+ |
| 32 | */ |
| 33 | |
| 34 | struct vr_lookup { |
| 35 | uint16_t mchid; |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 36 | uint8_t tdp; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 37 | uint32_t conf[NUM_VR_DOMAINS]; |
| 38 | }; |
| 39 | |
| 40 | static uint32_t load_table(const struct vr_lookup *tbl, const int tbl_entries, const int domain, |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 41 | const uint16_t mch_id, uint8_t tdp) |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 42 | { |
| 43 | for (size_t i = 0; i < tbl_entries; i++) { |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 44 | if (tbl[i].mchid != mch_id || tbl[i].tdp != tdp) |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 45 | continue; |
| 46 | return tbl[i].conf[domain]; |
| 47 | } |
| 48 | |
| 49 | printk(BIOS_ERR, "ERROR: Unknown MCH (0x%x) in %s\n", mch_id, __func__); |
| 50 | return 0; |
| 51 | } |
| 52 | |
Curtis Chen | 1f8563e | 2021-11-30 14:04:48 +0800 | [diff] [blame] | 53 | /* Per the power map from #613643, update ADL-P 6+8+2 (28W) VR configuration */ |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 54 | static const struct vr_lookup vr_config_ll[] = { |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 55 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 56 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
Curtis Chen | 1f8563e | 2021-11-30 14:04:48 +0800 | [diff] [blame] | 57 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 58 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, |
| 59 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
| 60 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 61 | }; |
| 62 | |
| 63 | static const struct vr_lookup vr_config_icc[] = { |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 64 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(120, 50) }, |
| 65 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_ICC(160, 50) }, |
Curtis Chen | 1f8563e | 2021-11-30 14:04:48 +0800 | [diff] [blame] | 66 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_ICC(111, 50) }, |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 67 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_ICC(85, 50) }, |
| 68 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
| 69 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | static const struct vr_lookup vr_config_tdc_timewindow[] = { |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 73 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 74 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Curtis Chen | 1f8563e | 2021-11-30 14:04:48 +0800 | [diff] [blame] | 75 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 76 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 77 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
| 78 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 79 | }; |
| 80 | |
| 81 | static const struct vr_lookup vr_config_tdc_currentlimit[] = { |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 82 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, |
| 83 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 57) }, |
Curtis Chen | 1f8563e | 2021-11-30 14:04:48 +0800 | [diff] [blame] | 84 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 85 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, |
| 86 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, |
| 87 | { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(20, 20) }, |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, |
| 91 | int domain, const struct vr_config *chip_cfg) |
| 92 | { |
| 93 | const struct vr_config *cfg; |
| 94 | |
| 95 | if (domain < 0 || domain >= NUM_VR_DOMAINS) |
| 96 | return; |
| 97 | |
| 98 | /* Use device tree override if requested */ |
| 99 | if (chip_cfg->vr_config_enable) { |
| 100 | cfg = chip_cfg; |
| 101 | |
Bora Guvendik | f6f1258 | 2021-09-02 13:23:03 -0700 | [diff] [blame] | 102 | if (cfg->ac_loadline) |
| 103 | s_cfg->AcLoadline[domain] = cfg->ac_loadline; |
| 104 | if (cfg->dc_loadline) |
| 105 | s_cfg->DcLoadline[domain] = cfg->dc_loadline; |
| 106 | if (cfg->icc_max) |
| 107 | s_cfg->IccMax[domain] = cfg->icc_max; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 108 | s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow; |
| 109 | s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 110 | } else { |
| 111 | uint16_t mch_id = 0; |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 112 | uint8_t tdp = get_cpu_tdp(); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 113 | |
| 114 | if (!mch_id) { |
| 115 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 116 | mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
| 117 | } |
| 118 | |
| 119 | s_cfg->AcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 120 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 121 | s_cfg->DcLoadline[domain] = load_table(vr_config_ll, ARRAY_SIZE(vr_config_ll), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 122 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 123 | s_cfg->IccMax[domain] = load_table(vr_config_icc, ARRAY_SIZE(vr_config_icc), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 124 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 125 | s_cfg->TdcTimeWindow[domain] = load_table(vr_config_tdc_timewindow, |
| 126 | ARRAY_SIZE(vr_config_tdc_timewindow), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 127 | domain, mch_id, tdp); |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 128 | s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit, |
| 129 | ARRAY_SIZE(vr_config_tdc_currentlimit), |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 130 | domain, mch_id, tdp); |
Ronak Kanabar | 1f88a71 | 2021-07-15 19:02:22 +0530 | [diff] [blame] | 131 | } |
| 132 | |
| 133 | /* Check TdcTimeWindow and TdcCurrentLimit, |
| 134 | Set TdcEnable and Set VR TDC Input current to root mean square */ |
| 135 | if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) { |
| 136 | s_cfg->TdcEnable[domain] = 1; |
| 137 | s_cfg->Irms[domain] = 1; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 138 | } |
| 139 | } |