Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 1 | struct syscall_result { |
| 2 | long val; |
| 3 | int errno; |
| 4 | }; |
| 5 | |
| 6 | static struct syscall_result syscall_return(long result) |
| 7 | { |
| 8 | struct syscall_result res; |
| 9 | if (((unsigned long)result) >= ((unsigned long)-125)) { |
| 10 | res.errno = - result; |
| 11 | res.val = -1; |
| 12 | } else { |
| 13 | res.errno = 0; |
| 14 | res.val = result; |
| 15 | } |
| 16 | return res; |
| 17 | } |
| 18 | |
| 19 | static struct syscall_result syscall0(unsigned long nr) |
| 20 | { |
| 21 | long res; |
| 22 | asm volatile( |
| 23 | "int $0x80" |
Eric Biederman | 8d9c123 | 2003-06-17 08:42:17 +0000 | [diff] [blame] | 24 | : "=a" (res) |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 25 | : "a" (nr)); |
| 26 | return syscall_return(res); |
| 27 | } |
| 28 | |
| 29 | static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) |
| 30 | { |
| 31 | long res; |
| 32 | asm volatile( |
| 33 | "int $0x80" |
Eric Biederman | 8d9c123 | 2003-06-17 08:42:17 +0000 | [diff] [blame] | 34 | : "=a" (res) |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 35 | : "a" (nr), "b" (arg1)); |
| 36 | return syscall_return(res); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 37 | |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) |
| 41 | { |
| 42 | long res; |
| 43 | asm volatile( |
| 44 | "int $0x80" |
Eric Biederman | 8d9c123 | 2003-06-17 08:42:17 +0000 | [diff] [blame] | 45 | : "=a" (res) |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 46 | : "a" (nr), "b" (arg1), "c" (arg2)); |
| 47 | return syscall_return(res); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 48 | |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | |
| 52 | static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, |
| 53 | unsigned long arg3) |
| 54 | { |
| 55 | long res; |
| 56 | asm volatile( |
| 57 | "int $0x80" |
Eric Biederman | 8d9c123 | 2003-06-17 08:42:17 +0000 | [diff] [blame] | 58 | : "=a" (res) |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 59 | : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); |
| 60 | return syscall_return(res); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 61 | |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 62 | } |
| 63 | |
| 64 | static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, |
| 65 | unsigned long arg3, unsigned long arg4) |
| 66 | { |
| 67 | long res; |
| 68 | asm volatile( |
| 69 | "int $0x80" |
Eric Biederman | 8d9c123 | 2003-06-17 08:42:17 +0000 | [diff] [blame] | 70 | : "=a" (res) |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 71 | : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); |
| 72 | return syscall_return(res); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 73 | |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 74 | } |
| 75 | |
| 76 | static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, |
| 77 | unsigned long arg3, unsigned long arg4, unsigned long arg5) |
| 78 | { |
| 79 | long res; |
| 80 | asm volatile( |
| 81 | "int $0x80" |
Eric Biederman | 8d9c123 | 2003-06-17 08:42:17 +0000 | [diff] [blame] | 82 | : "=a" (res) |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 83 | : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 84 | "S" (arg4), "D" (arg5)); |
| 85 | return syscall_return(res); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 86 | |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | #define NR_exit 1 |
| 90 | #define NR_fork 2 |
| 91 | #define NR_read 3 |
| 92 | #define NR_write 4 |
| 93 | #define NR_open 5 |
| 94 | #define NR_close 6 |
| 95 | #define NR_waitpid 7 |
| 96 | #define NR_creat 8 |
| 97 | #define NR_link 9 |
| 98 | #define NR_unlink 10 |
| 99 | #define NR_execve 11 |
| 100 | #define NR_chdir 12 |
| 101 | #define NR_time 13 |
| 102 | #define NR_mknod 14 |
| 103 | #define NR_chmod 15 |
| 104 | #define NR_lchown 16 |
| 105 | #define NR_break 17 |
| 106 | #define NR_oldstat 18 |
| 107 | #define NR_lseek 19 |
| 108 | #define NR_getpid 20 |
| 109 | #define NR_mount 21 |
| 110 | #define NR_umount 22 |
| 111 | #define NR_setuid 23 |
| 112 | #define NR_getuid 24 |
| 113 | #define NR_stime 25 |
| 114 | #define NR_ptrace 26 |
| 115 | #define NR_alarm 27 |
| 116 | #define NR_oldfstat 28 |
| 117 | #define NR_pause 29 |
| 118 | #define NR_utime 30 |
| 119 | #define NR_stty 31 |
| 120 | #define NR_gtty 32 |
| 121 | #define NR_access 33 |
| 122 | #define NR_nice 34 |
| 123 | #define NR_ftime 35 |
| 124 | #define NR_sync 36 |
| 125 | #define NR_kill 37 |
| 126 | #define NR_rename 38 |
| 127 | #define NR_mkdir 39 |
| 128 | #define NR_rmdir 40 |
| 129 | #define NR_dup 41 |
| 130 | #define NR_pipe 42 |
| 131 | #define NR_times 43 |
| 132 | #define NR_prof 44 |
| 133 | #define NR_brk 45 |
| 134 | #define NR_setgid 46 |
| 135 | #define NR_getgid 47 |
| 136 | #define NR_signal 48 |
| 137 | #define NR_geteuid 49 |
| 138 | #define NR_getegid 50 |
| 139 | #define NR_acct 51 |
| 140 | #define NR_umount2 52 |
| 141 | #define NR_lock 53 |
| 142 | #define NR_ioctl 54 |
| 143 | #define NR_fcntl 55 |
| 144 | #define NR_mpx 56 |
| 145 | #define NR_setpgid 57 |
| 146 | #define NR_ulimit 58 |
| 147 | #define NR_oldolduname 59 |
| 148 | #define NR_umask 60 |
| 149 | #define NR_chroot 61 |
| 150 | #define NR_ustat 62 |
| 151 | #define NR_dup2 63 |
| 152 | #define NR_getppid 64 |
| 153 | #define NR_getpgrp 65 |
| 154 | #define NR_setsid 66 |
| 155 | #define NR_sigaction 67 |
| 156 | #define NR_sgetmask 68 |
| 157 | #define NR_ssetmask 69 |
| 158 | #define NR_setreuid 70 |
| 159 | #define NR_setregid 71 |
| 160 | #define NR_sigsuspend 72 |
| 161 | #define NR_sigpending 73 |
| 162 | #define NR_sethostname 74 |
| 163 | #define NR_setrlimit 75 |
| 164 | #define NR_getrlimit 76 |
| 165 | #define NR_getrusage 77 |
| 166 | #define NR_gettimeofday 78 |
| 167 | #define NR_settimeofday 79 |
| 168 | #define NR_getgroups 80 |
| 169 | #define NR_setgroups 81 |
| 170 | #define NR_select 82 |
| 171 | #define NR_symlink 83 |
| 172 | #define NR_oldlstat 84 |
| 173 | #define NR_readlink 85 |
| 174 | #define NR_uselib 86 |
| 175 | #define NR_swapon 87 |
| 176 | #define NR_reboot 88 |
| 177 | #define NR_readdir 89 |
| 178 | #define NR_mmap 90 |
| 179 | #define NR_munmap 91 |
| 180 | #define NR_truncate 92 |
| 181 | #define NR_ftruncate 93 |
| 182 | #define NR_fchmod 94 |
| 183 | #define NR_fchown 95 |
| 184 | #define NR_getpriority 96 |
| 185 | #define NR_setpriority 97 |
| 186 | #define NR_profil 98 |
| 187 | #define NR_statfs 99 |
| 188 | #define NR_fstatfs 100 |
| 189 | #define NR_ioperm 101 |
| 190 | #define NR_socketcall 102 |
| 191 | #define NR_syslog 103 |
| 192 | #define NR_setitimer 104 |
| 193 | #define NR_getitimer 105 |
| 194 | #define NR_stat 106 |
| 195 | #define NR_lstat 107 |
| 196 | #define NR_fstat 108 |
| 197 | #define NR_olduname 109 |
| 198 | #define NR_iopl 110 |
| 199 | #define NR_vhangup 111 |
| 200 | #define NR_idle 112 |
| 201 | #define NR_vm86old 113 |
| 202 | #define NR_wait4 114 |
| 203 | #define NR_swapoff 115 |
| 204 | #define NR_sysinfo 116 |
| 205 | #define NR_ipc 117 |
| 206 | #define NR_fsync 118 |
| 207 | #define NR_sigreturn 119 |
| 208 | #define NR_clone 120 |
| 209 | #define NR_setdomainname 121 |
| 210 | #define NR_uname 122 |
| 211 | #define NR_modify_ldt 123 |
| 212 | #define NR_adjtimex 124 |
| 213 | #define NR_mprotect 125 |
| 214 | #define NR_sigprocmask 126 |
| 215 | #define NR_create_module 127 |
| 216 | #define NR_init_module 128 |
| 217 | #define NR_delete_module 129 |
| 218 | #define NR_get_kernel_syms 130 |
| 219 | #define NR_quotactl 131 |
| 220 | #define NR_getpgid 132 |
| 221 | #define NR_fchdir 133 |
| 222 | #define NR_bdflush 134 |
| 223 | #define NR_sysfs 135 |
| 224 | #define NR_personality 136 |
| 225 | #define NR_afs_syscall 137 /* Syscall for Andrew File System */ |
| 226 | #define NR_setfsuid 138 |
| 227 | #define NR_setfsgid 139 |
| 228 | #define NR__llseek 140 |
| 229 | #define NR_getdents 141 |
| 230 | #define NR__newselect 142 |
| 231 | #define NR_flock 143 |
| 232 | #define NR_msync 144 |
| 233 | #define NR_readv 145 |
| 234 | #define NR_writev 146 |
| 235 | #define NR_getsid 147 |
| 236 | #define NR_fdatasync 148 |
| 237 | #define NR__sysctl 149 |
| 238 | #define NR_mlock 150 |
| 239 | #define NR_munlock 151 |
| 240 | #define NR_mlockall 152 |
| 241 | #define NR_munlockall 153 |
| 242 | #define NR_sched_setparam 154 |
| 243 | #define NR_sched_getparam 155 |
| 244 | #define NR_sched_setscheduler 156 |
| 245 | #define NR_sched_getscheduler 157 |
| 246 | #define NR_sched_yield 158 |
| 247 | #define NR_sched_get_priority_max 159 |
| 248 | #define NR_sched_get_priority_min 160 |
| 249 | #define NR_sched_rr_get_interval 161 |
| 250 | #define NR_nanosleep 162 |
| 251 | #define NR_mremap 163 |
| 252 | #define NR_setresuid 164 |
| 253 | #define NR_getresuid 165 |
| 254 | #define NR_vm86 166 |
| 255 | #define NR_query_module 167 |
| 256 | #define NR_poll 168 |
| 257 | #define NR_nfsservctl 169 |
| 258 | #define NR_setresgid 170 |
| 259 | #define NR_getresgid 171 |
| 260 | #define NR_prctl 172 |
| 261 | #define NR_rt_sigreturn 173 |
| 262 | #define NR_rt_sigaction 174 |
| 263 | #define NR_rt_sigprocmask 175 |
| 264 | #define NR_rt_sigpending 176 |
| 265 | #define NR_rt_sigtimedwait 177 |
| 266 | #define NR_rt_sigqueueinfo 178 |
| 267 | #define NR_rt_sigsuspend 179 |
| 268 | #define NR_pread 180 |
| 269 | #define NR_pwrite 181 |
| 270 | #define NR_chown 182 |
| 271 | #define NR_getcwd 183 |
| 272 | #define NR_capget 184 |
| 273 | #define NR_capset 185 |
| 274 | #define NR_sigaltstack 186 |
| 275 | #define NR_sendfile 187 |
| 276 | #define NR_getpmsg 188 /* some people actually want streams */ |
| 277 | #define NR_putpmsg 189 /* some people actually want streams */ |
| 278 | #define NR_vfork 190 |
| 279 | |
| 280 | typedef long ssize_t; |
| 281 | typedef unsigned long size_t; |
| 282 | |
| 283 | /* Standard file descriptors */ |
| 284 | #define STDIN_FILENO 0 /* Standard input */ |
| 285 | #define STDOUT_FILENO 1 /* Standard output */ |
| 286 | #define STDERR_FILENO 2 /* Standard error output */ |
| 287 | |
| 288 | static ssize_t write(int fd, const void *buf, size_t count) |
| 289 | { |
| 290 | struct syscall_result res; |
| 291 | res = syscall3(NR_write, fd, (unsigned long)buf, count); |
| 292 | return res.val; |
| 293 | } |
| 294 | |
| 295 | static void _exit(int status) |
| 296 | { |
| 297 | struct syscall_result res; |
| 298 | res = syscall1(NR_exit, status); |
| 299 | } |
| 300 | |
| 301 | static const char *addr_of_char(unsigned char ch) |
| 302 | { |
| 303 | static const char byte[] = { |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 304 | 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 305 | 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 306 | 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 307 | 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 308 | 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 309 | 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 310 | 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 311 | 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 312 | 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 313 | 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 314 | 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 315 | 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 316 | 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 317 | 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 318 | 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 319 | 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 320 | 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 321 | 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 322 | 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 323 | 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 324 | 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 325 | 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 326 | 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 327 | 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 328 | 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 329 | 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 330 | 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 331 | 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 332 | 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 333 | 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 334 | 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 335 | 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, |
| 336 | }; |
| 337 | return byte + ch; |
| 338 | } |
| 339 | |
| 340 | static void console_tx_byte(unsigned char ch) |
| 341 | { |
| 342 | write(STDOUT_FILENO, addr_of_char(ch), 1); |
| 343 | } |
| 344 | |
| 345 | static void console_tx_nibble(unsigned nibble) |
| 346 | { |
| 347 | unsigned char digit; |
| 348 | digit = nibble + '0'; |
| 349 | if (digit > '9') { |
| 350 | digit += 39; |
| 351 | } |
| 352 | console_tx_byte(digit); |
| 353 | } |
| 354 | |
| 355 | static void console_tx_char(unsigned char byte) |
| 356 | { |
| 357 | console_tx_byte(byte); |
| 358 | } |
| 359 | |
| 360 | static void console_tx_hex8(unsigned char value) |
| 361 | { |
| 362 | console_tx_nibble((value >> 4U) & 0x0fU); |
| 363 | console_tx_nibble(value & 0x0fU); |
| 364 | } |
| 365 | |
| 366 | static void console_tx_hex16(unsigned short value) |
| 367 | { |
| 368 | console_tx_nibble((value >> 12U) & 0x0FU); |
| 369 | console_tx_nibble((value >> 8U) & 0x0FU); |
| 370 | console_tx_nibble((value >> 4U) & 0x0FU); |
| 371 | console_tx_nibble(value & 0x0FU); |
| 372 | } |
| 373 | |
| 374 | static void console_tx_hex32(unsigned short value) |
| 375 | { |
| 376 | console_tx_nibble((value >> 28U) & 0x0FU); |
| 377 | console_tx_nibble((value >> 24U) & 0x0FU); |
| 378 | console_tx_nibble((value >> 20U) & 0x0FU); |
| 379 | console_tx_nibble((value >> 16U) & 0x0FU); |
| 380 | console_tx_nibble((value >> 12U) & 0x0FU); |
| 381 | console_tx_nibble((value >> 8U) & 0x0FU); |
| 382 | console_tx_nibble((value >> 4U) & 0x0FU); |
| 383 | console_tx_nibble(value & 0x0FU); |
| 384 | } |
| 385 | |
| 386 | static void console_tx_string(const char *str) |
| 387 | { |
| 388 | unsigned char ch; |
| 389 | while((ch = *str++) != '\0') { |
| 390 | console_tx_byte(ch); |
| 391 | } |
| 392 | } |
| 393 | |
| 394 | static void print_debug_char(unsigned char byte) { console_tx_char(byte); } |
| 395 | static void print_debug_hex8(unsigned char value) { console_tx_hex8(value); } |
| 396 | static void print_debug_hex16(unsigned short value){ console_tx_hex16(value); } |
| 397 | static void print_debug_hex32(unsigned int value) { console_tx_hex32(value); } |
| 398 | static void print_debug(const char *str) { console_tx_string(str); } |
| 399 | |
| 400 | |
| 401 | static void setup_coherent_ht_domain(void) |
| 402 | { |
| 403 | static const unsigned int register_values[] = { |
| 404 | #if 1 |
| 405 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101, |
| 406 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101, |
| 407 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101, |
| 408 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101, |
| 409 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101, |
| 410 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101, |
| 411 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101, |
| 412 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101, |
| 413 | # 983 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 414 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f, |
| 415 | # 1005 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 416 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4), |
| 417 | # 1082 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 418 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020, |
| 419 | # 1127 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 420 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200, |
| 421 | # 1148 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 422 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000, |
| 423 | # 1182 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 424 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000, |
| 425 | |
| 426 | |
| 427 | |
| 428 | |
| 429 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001, |
| 430 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002, |
| 431 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003, |
| 432 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004, |
| 433 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005, |
| 434 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006, |
| 435 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007, |
| 436 | # 1224 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 437 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003, |
| 438 | |
| 439 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000, |
| 440 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000, |
| 441 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000, |
| 442 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000, |
| 443 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000, |
| 444 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000, |
| 445 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000, |
| 446 | # 1276 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 447 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00, |
| 448 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00, |
| 449 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00, |
| 450 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000, |
| 451 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000, |
| 452 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000, |
| 453 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00, |
| 454 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00, |
| 455 | # 1311 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 456 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003, |
| 457 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003, |
| 458 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003, |
| 459 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000, |
| 460 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000, |
| 461 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000, |
| 462 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03, |
| 463 | |
| 464 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003, |
| 465 | # 1350 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 466 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000, |
| 467 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000, |
| 468 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000, |
| 469 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000, |
| 470 | # 1380 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 471 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003, |
| 472 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013, |
| 473 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000, |
| 474 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000, |
| 475 | # 1421 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" |
| 476 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003, |
| 477 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000, |
| 478 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000, |
| 479 | ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000, |
| 480 | #else |
| 481 | #define PCI_ADDR(BUS, DEV, FN, WHERE) ( \ |
| 482 | (((BUS) & 0xFF) << 16) | \ |
| 483 | (((DEV) & 0x1f) << 11) | \ |
| 484 | (((FN) & 0x07) << 8) | \ |
| 485 | ((WHERE) & 0xFF)) |
| 486 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 487 | /* Routing Table Node i |
| 488 | * F0:0x40 i = 0, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 489 | * F0:0x44 i = 1, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 490 | * F0:0x48 i = 2, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 491 | * F0:0x4c i = 3, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 492 | * F0:0x50 i = 4, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 493 | * F0:0x54 i = 5, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 494 | * F0:0x58 i = 6, |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 495 | * F0:0x5c i = 7 |
| 496 | * [ 0: 3] Request Route |
| 497 | * [0] Route to this node |
| 498 | * [1] Route to Link 0 |
| 499 | * [2] Route to Link 1 |
| 500 | * [3] Route to Link 2 |
| 501 | * [11: 8] Response Route |
| 502 | * [0] Route to this node |
| 503 | * [1] Route to Link 0 |
| 504 | * [2] Route to Link 1 |
| 505 | * [3] Route to Link 2 |
| 506 | * [19:16] Broadcast route |
| 507 | * [0] Route to this node |
| 508 | * [1] Route to Link 0 |
| 509 | * [2] Route to Link 1 |
| 510 | * [3] Route to Link 2 |
| 511 | */ |
| 512 | PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00010101, |
| 513 | PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010101, |
| 514 | PCI_ADDR(0, 0x18, 0, 0x48), 0xfff0f0f0, 0x00010101, |
| 515 | PCI_ADDR(0, 0x18, 0, 0x4c), 0xfff0f0f0, 0x00010101, |
| 516 | PCI_ADDR(0, 0x18, 0, 0x50), 0xfff0f0f0, 0x00010101, |
| 517 | PCI_ADDR(0, 0x18, 0, 0x54), 0xfff0f0f0, 0x00010101, |
| 518 | PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101, |
| 519 | PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101, |
| 520 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 521 | /* Hypetransport Transaction Control Register |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 522 | * F0:0x68 |
| 523 | * [ 0: 0] Disable read byte probe |
| 524 | * 0 = Probes issues |
| 525 | * 1 = Probes not issued |
| 526 | * [ 1: 1] Disable Read Doubleword probe |
| 527 | * 0 = Probes issued |
| 528 | * 1 = Probes not issued |
| 529 | * [ 2: 2] Disable write byte probes |
| 530 | * 0 = Probes issued |
| 531 | * 1 = Probes not issued |
| 532 | * [ 3: 3] Disable Write Doubleword Probes |
| 533 | * 0 = Probes issued |
| 534 | * 1 = Probes not issued. |
| 535 | * [ 4: 4] Disable Memroy Controller Target Start |
| 536 | * 0 = TgtStart packets are generated |
| 537 | * 1 = TgtStart packets are not generated. |
| 538 | * [ 5: 5] CPU1 Enable |
| 539 | * 0 = Second CPU disabled or not present |
| 540 | * 1 = Second CPU enabled. |
| 541 | * [ 6: 6] CPU Request PassPW |
| 542 | * 0 = CPU requests do not pass posted writes |
| 543 | * 1 = CPU requests pass posted writes. |
| 544 | * [ 7: 7] CPU read Respons PassPW |
| 545 | * 0 = CPU Responses do not pass posted writes |
| 546 | * 1 = CPU responses pass posted writes. |
| 547 | * [ 8: 8] Disable Probe Memory Cancel |
| 548 | * 0 = Probes may generate MemCancels |
| 549 | * 1 = Probes may not generate MemCancels |
| 550 | * [ 9: 9] Disable Remote Probe Memory Cancel. |
| 551 | * 0 = Probes hitting dirty blocks generate memory cancel packets |
| 552 | * 1 = Only probed caches on the same node as the memory controller |
| 553 | * generate cancel packets. |
| 554 | * [10:10] Disable Fill Probe |
| 555 | * 0 = Probes issued for cache fills |
| 556 | * 1 = Probes not issued for cache fills. |
| 557 | * [11:11] Response PassPw |
| 558 | * 0 = Downstream response PassPW based on original request |
| 559 | * 1 = Downstream response PassPW set to 1 |
| 560 | * [12:12] Change ISOC to Ordered |
| 561 | * 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization |
| 562 | * 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 563 | * [14:13] Buffer Release Priority select |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 564 | * 00 = 64 |
| 565 | * 01 = 16 |
| 566 | * 10 = 8 |
| 567 | * 11 = 2 |
| 568 | * [15:15] Limit Coherent HT Configuration Space Range |
| 569 | * 0 = No coherent HT configuration space restrictions |
| 570 | * 1 = Limit coherent HT configuration space based on node count |
| 571 | * [16:16] Local Interrupt Conversion Enable. |
| 572 | * 0 = ExtInt/NMI interrups unaffected. |
| 573 | * 1 = ExtInt/NMI broadcat interrupts converted to LINT0/1 |
| 574 | * [17:17] APIC Extended Broadcast Enable. |
| 575 | * 0 = APIC broadcast is 0F |
| 576 | * 1 = APIC broadcast is FF |
| 577 | * [18:18] APIC Extended ID Enable |
| 578 | * 0 = APIC ID is 4 bits. |
| 579 | * 1 = APIC ID is 8 bits. |
| 580 | * [19:19] APIC Extended Spurious Vector Enable |
| 581 | * 0 = Lower 4 bits of spurious vector are read-only 1111 |
| 582 | * 1 = Lower 4 bits of spurious vecotr are writeable. |
| 583 | * [20:20] Sequence ID Source Node Enable |
| 584 | * 0 = Normal operation |
| 585 | * 1 = Keep SeqID on routed packets for debugging. |
| 586 | * [22:21] Downstream non-posted request limit |
| 587 | * 00 = No limit |
| 588 | * 01 = Limited to 1 |
| 589 | * 10 = Limited to 4 |
| 590 | * 11 = Limited to 8 |
| 591 | * [23:23] RESERVED |
| 592 | * [25:24] Medium-Priority Bypass Count |
| 593 | * - Maximum # of times a medium priority access can pass a low |
| 594 | * priority access before Medium-Priority mode is disabled for one access. |
| 595 | * [27:26] High-Priority Bypass Count |
| 596 | * - Maximum # of times a high prioirty access can pass a medium or low |
| 597 | * priority access before High-prioirty mode is disabled for one access. |
| 598 | * [28:28] Enable High Priority CPU Reads |
| 599 | * 0 = Cpu reads are medium prioirty |
| 600 | * 1 = Cpu reads are high prioirty |
| 601 | * [29:29] Disable Low Priority Writes |
| 602 | * 0 = Non-isochronous writes are low priority |
| 603 | * 1 = Non-isochronous writes are medium prioirty |
| 604 | * [30:30] Disable High Priority Isochronous writes |
| 605 | * 0 = Isochronous writes are high priority |
| 606 | * 1 = Isochronous writes are medium priority |
| 607 | * [31:31] Disable Medium Priority Isochronous writes |
| 608 | * 0 = Isochronous writes are medium are high |
| 609 | * 1 = With bit 30 set makes Isochrouns writes low priority. |
| 610 | */ |
| 611 | PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00840f, |
| 612 | /* HT Initialization Control Register |
| 613 | * F0:0x6C |
| 614 | * [ 0: 0] Routing Table Disable |
| 615 | * 0 = Packets are routed according to routing tables |
| 616 | * 1 = Packets are routed according to the default link field |
| 617 | * [ 1: 1] Request Disable (BSP should clear this) |
| 618 | * 0 = Request packets may be generated |
| 619 | * 1 = Request packets may not be generated. |
| 620 | * [ 3: 2] Default Link (Read-only) |
| 621 | * 00 = LDT0 |
| 622 | * 01 = LDT1 |
| 623 | * 10 = LDT2 |
| 624 | * 11 = CPU on same node |
| 625 | * [ 4: 4] Cold Reset |
| 626 | * - Scratch bit cleared by a cold reset |
| 627 | * [ 5: 5] BIOS Reset Detect |
| 628 | * - Scratch bit cleared by a cold reset |
| 629 | * [ 6: 6] INIT Detect |
| 630 | * - Scratch bit cleared by a warm or cold reset not by an INIT |
| 631 | * |
| 632 | */ |
| 633 | PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4), |
| 634 | /* LDTi Capabilities Registers |
| 635 | * F0:0x80 i = 0, |
| 636 | * F0:0xA0 i = 1, |
| 637 | * F0:0xC0 i = 2, |
| 638 | */ |
| 639 | /* LDTi Link Control Registrs |
| 640 | * F0:0x84 i = 0, |
| 641 | * F0:0xA4 i = 1, |
| 642 | * F0:0xC4 i = 2, |
| 643 | * [ 1: 1] CRC Flood Enable |
| 644 | * 0 = Do not generate sync packets on CRC error |
| 645 | * 1 = Generate sync packets on CRC error |
| 646 | * [ 2: 2] CRC Start Test (Read-Only) |
| 647 | * [ 3: 3] CRC Force Frame Error |
| 648 | * 0 = Do not generate bad CRC |
| 649 | * 1 = Generate bad CRC |
| 650 | * [ 4: 4] Link Failure |
| 651 | * 0 = No link failure detected |
| 652 | * 1 = Link failure detected |
| 653 | * [ 5: 5] Initialization Complete |
| 654 | * 0 = Initialization not complete |
| 655 | * 1 = Initialization complete |
| 656 | * [ 6: 6] Receiver off |
| 657 | * 0 = Recevier on |
| 658 | * 1 = Receiver off |
| 659 | * [ 7: 7] Transmitter Off |
| 660 | * 0 = Transmitter on |
| 661 | * 1 = Transmitter off |
| 662 | * [ 9: 8] CRC_Error |
| 663 | * 00 = No error |
| 664 | * [0] = 1 Error on byte lane 0 |
| 665 | * [1] = 1 Error on byte lane 1 |
| 666 | * [12:12] Isochrnous Enable (Read-Only) |
| 667 | * [13:13] HT Stop Tristate Enable |
| 668 | * 0 = Driven during an LDTSTOP_L |
| 669 | * 1 = Tristated during and LDTSTOP_L |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 670 | * [14:14] Extended CTL Time |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 671 | * 0 = CTL is asserted for 16 bit times during link initialization |
| 672 | * 1 = CTL is asserted for 50us during link initialization |
| 673 | * [18:16] Max Link Width In (Read-Only?) |
| 674 | * 000 = 8 bit link |
| 675 | * 001 = 16bit link |
| 676 | * [19:19] Doubleword Flow Control in (Read-Only) |
| 677 | * 0 = This link does not support doubleword flow control |
| 678 | * 1 = This link supports doubleword flow control |
| 679 | * [22:20] Max Link Width Out (Read-Only?) |
| 680 | * 000 = 8 bit link |
| 681 | * 001 = 16bit link |
| 682 | * [23:23] Doubleworld Flow Control out (Read-Only) |
| 683 | * 0 = This link does not support doubleword flow control |
| 684 | * 1 = This link supports doubleworkd flow control |
| 685 | * [26:24] Link Width In |
| 686 | * 000 = Use 8 bits |
| 687 | * 001 = Use 16 bits |
| 688 | * 010 = reserved |
| 689 | * 011 = Use 32 bits |
| 690 | * 100 = Use 2 bits |
| 691 | * 101 = Use 4 bits |
| 692 | * 110 = reserved |
| 693 | * 111 = Link physically not connected |
| 694 | * [27:27] Doubleword Flow Control In Enable |
| 695 | * 0 = Doubleword flow control disabled |
| 696 | * 1 = Doubleword flow control enabled (Not currently supported) |
| 697 | * [30:28] Link Width Out |
| 698 | * 000 = Use 8 bits |
| 699 | * 001 = Use 16 bits |
| 700 | * 010 = reserved |
| 701 | * 011 = Use 32 bits |
| 702 | * 100 = Use 2 bits |
| 703 | * 101 = Use 4 bits |
| 704 | * 110 = reserved |
| 705 | * 111 = Link physically not connected |
| 706 | * [31:31] Doubleworld Flow Control Out Enable |
| 707 | * 0 = Doubleworld flow control disabled |
| 708 | * 1 = Doubleword flow control enabled (Not currently supported) |
| 709 | */ |
| 710 | PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020, |
| 711 | /* LDTi Frequency/Revision Registers |
| 712 | * F0:0x88 i = 0, |
| 713 | * F0:0xA8 i = 1, |
| 714 | * F0:0xC8 i = 2, |
| 715 | * [ 4: 0] Minor Revision |
| 716 | * Contains the HT Minor revision |
| 717 | * [ 7: 5] Major Revision |
| 718 | * Contains the HT Major revision |
| 719 | * [11: 8] Link Frequency (Takes effect the next time the link is reconnected) |
| 720 | * 0000 = 200Mhz |
| 721 | * 0001 = reserved |
| 722 | * 0010 = 400Mhz |
| 723 | * 0011 = reserved |
| 724 | * 0100 = 600Mhz |
| 725 | * 0101 = 800Mhz |
| 726 | * 0110 = 1000Mhz |
| 727 | * 0111 = reserved |
| 728 | * 1000 = reserved |
| 729 | * 1001 = reserved |
| 730 | * 1010 = reserved |
| 731 | * 1011 = reserved |
| 732 | * 1100 = reserved |
| 733 | * 1101 = reserved |
| 734 | * 1110 = reserved |
| 735 | * 1111 = 100 Mhz |
| 736 | * [15:12] Error (Not currently Implemented) |
| 737 | * [31:16] Indicates the frequency capabilities of the link |
| 738 | * [16] = 1 encoding 0000 of freq supported |
| 739 | * [17] = 1 encoding 0001 of freq supported |
| 740 | * [18] = 1 encoding 0010 of freq supported |
| 741 | * [19] = 1 encoding 0011 of freq supported |
| 742 | * [20] = 1 encoding 0100 of freq supported |
| 743 | * [21] = 1 encoding 0101 of freq supported |
| 744 | * [22] = 1 encoding 0110 of freq supported |
| 745 | * [23] = 1 encoding 0111 of freq supported |
| 746 | * [24] = 1 encoding 1000 of freq supported |
| 747 | * [25] = 1 encoding 1001 of freq supported |
| 748 | * [26] = 1 encoding 1010 of freq supported |
| 749 | * [27] = 1 encoding 1011 of freq supported |
| 750 | * [28] = 1 encoding 1100 of freq supported |
| 751 | * [29] = 1 encoding 1101 of freq supported |
| 752 | * [30] = 1 encoding 1110 of freq supported |
| 753 | * [31] = 1 encoding 1111 of freq supported |
| 754 | */ |
| 755 | PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000200, |
| 756 | /* LDTi Feature Capability |
| 757 | * F0:0x8C i = 0, |
| 758 | * F0:0xAC i = 1, |
| 759 | * F0:0xCC i = 2, |
| 760 | */ |
| 761 | /* LDTi Buffer Count Registers |
| 762 | * F0:0x90 i = 0, |
| 763 | * F0:0xB0 i = 1, |
| 764 | * F0:0xD0 i = 2, |
| 765 | */ |
| 766 | /* LDTi Bus Number Registers |
| 767 | * F0:0x94 i = 0, |
| 768 | * F0:0xB4 i = 1, |
| 769 | * F0:0xD4 i = 2, |
| 770 | * For NonCoherent HT specifies the bus number downstream (behind the host bridge) |
| 771 | * [ 0: 7] Primary Bus Number |
| 772 | * [15: 8] Secondary Bus Number |
| 773 | * [23:15] Subordiante Bus Number |
| 774 | * [31:24] reserved |
| 775 | */ |
| 776 | PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000, |
| 777 | /* LDTi Type Registers |
| 778 | * F0:0x98 i = 0, |
| 779 | * F0:0xB8 i = 1, |
| 780 | * F0:0xD8 i = 2, |
| 781 | */ |
| 782 | /* Careful set limit registers before base registers which contain the enables */ |
| 783 | /* DRAM Limit i Registers |
| 784 | * F1:0x44 i = 0 |
| 785 | * F1:0x4C i = 1 |
| 786 | * F1:0x54 i = 2 |
| 787 | * F1:0x5C i = 3 |
| 788 | * F1:0x64 i = 4 |
| 789 | * F1:0x6C i = 5 |
| 790 | * F1:0x74 i = 6 |
| 791 | * F1:0x7C i = 7 |
| 792 | * [ 2: 0] Destination Node ID |
| 793 | * 000 = Node 0 |
| 794 | * 001 = Node 1 |
| 795 | * 010 = Node 2 |
| 796 | * 011 = Node 3 |
| 797 | * 100 = Node 4 |
| 798 | * 101 = Node 5 |
| 799 | * 110 = Node 6 |
| 800 | * 111 = Node 7 |
| 801 | * [ 7: 3] Reserved |
| 802 | * [10: 8] Interleave select |
| 803 | * specifies the values of A[14:12] to use with interleave enable. |
| 804 | * [15:11] Reserved |
| 805 | * [31:16] DRAM Limit Address i Bits 39-24 |
| 806 | * This field defines the upper address bits of a 40 bit address |
| 807 | * that define the end of the DRAM region. |
| 808 | */ |
| 809 | #if MEMORY_1024MB |
| 810 | PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000, |
| 811 | #endif |
| 812 | #if MEMORY_512MB |
| 813 | PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000, |
| 814 | #endif |
| 815 | PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, |
| 816 | PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, |
| 817 | PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, |
| 818 | PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, |
| 819 | PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, |
| 820 | PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, |
| 821 | PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, |
| 822 | /* DRAM Base i Registers |
| 823 | * F1:0x40 i = 0 |
| 824 | * F1:0x48 i = 1 |
| 825 | * F1:0x50 i = 2 |
| 826 | * F1:0x58 i = 3 |
| 827 | * F1:0x60 i = 4 |
| 828 | * F1:0x68 i = 5 |
| 829 | * F1:0x70 i = 6 |
| 830 | * F1:0x78 i = 7 |
| 831 | * [ 0: 0] Read Enable |
| 832 | * 0 = Reads Disabled |
| 833 | * 1 = Reads Enabled |
| 834 | * [ 1: 1] Write Enable |
| 835 | * 0 = Writes Disabled |
| 836 | * 1 = Writes Enabled |
| 837 | * [ 7: 2] Reserved |
| 838 | * [10: 8] Interleave Enable |
| 839 | * 000 = No interleave |
| 840 | * 001 = Interleave on A[12] (2 nodes) |
| 841 | * 010 = reserved |
| 842 | * 011 = Interleave on A[12] and A[14] (4 nodes) |
| 843 | * 100 = reserved |
| 844 | * 101 = reserved |
| 845 | * 110 = reserved |
| 846 | * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) |
| 847 | * [15:11] Reserved |
| 848 | * [13:16] DRAM Base Address i Bits 39-24 |
| 849 | * This field defines the upper address bits of a 40-bit address |
| 850 | * that define the start of the DRAM region. |
| 851 | */ |
| 852 | PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003, |
| 853 | #if MEMORY_1024MB |
| 854 | PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000, |
| 855 | PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000, |
| 856 | PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000, |
| 857 | PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000, |
| 858 | PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000, |
| 859 | PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000, |
| 860 | PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000, |
| 861 | #endif |
| 862 | #if MEMORY_512MB |
| 863 | PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000, |
| 864 | PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000, |
| 865 | PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000, |
| 866 | PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000, |
| 867 | PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000, |
| 868 | PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000, |
| 869 | PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000, |
| 870 | #endif |
| 871 | |
| 872 | /* Memory-Mapped I/O Limit i Registers |
| 873 | * F1:0x84 i = 0 |
| 874 | * F1:0x8C i = 1 |
| 875 | * F1:0x94 i = 2 |
| 876 | * F1:0x9C i = 3 |
| 877 | * F1:0xA4 i = 4 |
| 878 | * F1:0xAC i = 5 |
| 879 | * F1:0xB4 i = 6 |
| 880 | * F1:0xBC i = 7 |
| 881 | * [ 2: 0] Destination Node ID |
| 882 | * 000 = Node 0 |
| 883 | * 001 = Node 1 |
| 884 | * 010 = Node 2 |
| 885 | * 011 = Node 3 |
| 886 | * 100 = Node 4 |
| 887 | * 101 = Node 5 |
| 888 | * 110 = Node 6 |
| 889 | * 111 = Node 7 |
| 890 | * [ 3: 3] Reserved |
| 891 | * [ 5: 4] Destination Link ID |
| 892 | * 00 = Link 0 |
| 893 | * 01 = Link 1 |
| 894 | * 10 = Link 2 |
| 895 | * 11 = Reserved |
| 896 | * [ 6: 6] Reserved |
| 897 | * [ 7: 7] Non-Posted |
| 898 | * 0 = CPU writes may be posted |
| 899 | * 1 = CPU writes must be non-posted |
| 900 | * [31: 8] Memory-Mapped I/O Limit Address i (39-16) |
| 901 | * This field defines the upp adddress bits of a 40-bit address that |
| 902 | * defines the end of a memory-mapped I/O region n |
| 903 | */ |
| 904 | PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00, |
| 905 | PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00, |
| 906 | PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00, |
| 907 | PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, |
| 908 | PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, |
| 909 | PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, |
| 910 | PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00, |
| 911 | PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00, |
| 912 | |
| 913 | /* Memory-Mapped I/O Base i Registers |
| 914 | * F1:0x80 i = 0 |
| 915 | * F1:0x88 i = 1 |
| 916 | * F1:0x90 i = 2 |
| 917 | * F1:0x98 i = 3 |
| 918 | * F1:0xA0 i = 4 |
| 919 | * F1:0xA8 i = 5 |
| 920 | * F1:0xB0 i = 6 |
| 921 | * F1:0xB8 i = 7 |
| 922 | * [ 0: 0] Read Enable |
| 923 | * 0 = Reads disabled |
| 924 | * 1 = Reads Enabled |
| 925 | * [ 1: 1] Write Enable |
| 926 | * 0 = Writes disabled |
| 927 | * 1 = Writes Enabled |
| 928 | * [ 2: 2] Cpu Disable |
| 929 | * 0 = Cpu can use this I/O range |
| 930 | * 1 = Cpu requests do not use this I/O range |
| 931 | * [ 3: 3] Lock |
| 932 | * 0 = base/limit registers i are read/write |
| 933 | * 1 = base/limit registers i are read-only |
| 934 | * [ 7: 4] Reserved |
| 935 | * [31: 8] Memory-Mapped I/O Base Address i (39-16) |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 936 | * This field defines the upper address bits of a 40bit address |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 937 | * that defines the start of memory-mapped I/O region i |
| 938 | */ |
| 939 | PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003, |
| 940 | PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003, |
| 941 | PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003, |
| 942 | PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, |
| 943 | PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, |
| 944 | PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, |
| 945 | PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03, |
| 946 | #if MEMORY_1024MB |
| 947 | PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003, |
| 948 | #endif |
| 949 | #if MEMORY_512MB |
| 950 | PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003, |
| 951 | #endif |
| 952 | |
| 953 | /* PCI I/O Limit i Registers |
| 954 | * F1:0xC4 i = 0 |
| 955 | * F1:0xCC i = 1 |
| 956 | * F1:0xD4 i = 2 |
| 957 | * F1:0xDC i = 3 |
| 958 | * [ 2: 0] Destination Node ID |
| 959 | * 000 = Node 0 |
| 960 | * 001 = Node 1 |
| 961 | * 010 = Node 2 |
| 962 | * 011 = Node 3 |
| 963 | * 100 = Node 4 |
| 964 | * 101 = Node 5 |
| 965 | * 110 = Node 6 |
| 966 | * 111 = Node 7 |
| 967 | * [ 3: 3] Reserved |
| 968 | * [ 5: 4] Destination Link ID |
| 969 | * 00 = Link 0 |
| 970 | * 01 = Link 1 |
| 971 | * 10 = Link 2 |
| 972 | * 11 = reserved |
| 973 | * [11: 6] Reserved |
| 974 | * [24:12] PCI I/O Limit Address i |
| 975 | * This field defines the end of PCI I/O region n |
| 976 | * [31:25] Reserved |
| 977 | */ |
| 978 | PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000, |
| 979 | PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000, |
| 980 | PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, |
| 981 | PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, |
| 982 | |
| 983 | /* PCI I/O Base i Registers |
| 984 | * F1:0xC0 i = 0 |
| 985 | * F1:0xC8 i = 1 |
| 986 | * F1:0xD0 i = 2 |
| 987 | * F1:0xD8 i = 3 |
| 988 | * [ 0: 0] Read Enable |
| 989 | * 0 = Reads Disabled |
| 990 | * 1 = Reads Enabled |
| 991 | * [ 1: 1] Write Enable |
| 992 | * 0 = Writes Disabled |
| 993 | * 1 = Writes Enabled |
| 994 | * [ 3: 2] Reserved |
| 995 | * [ 4: 4] VGA Enable |
| 996 | * 0 = VGA matches Disabled |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 997 | * 1 = matches all address < 64K and where A[9:0] is in the |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 998 | * range 3B0-3BB or 3C0-3DF independen of the base & limit registers |
| 999 | * [ 5: 5] ISA Enable |
| 1000 | * 0 = ISA matches Disabled |
| 1001 | * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block |
| 1002 | * from matching agains this base/limit pair |
| 1003 | * [11: 6] Reserved |
| 1004 | * [24:12] PCI I/O Base i |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 1005 | * This field defines the start of PCI I/O region n |
Eric Biederman | 6aa31cc | 2003-06-10 21:22:07 +0000 | [diff] [blame] | 1006 | * [31:25] Reserved |
| 1007 | */ |
| 1008 | PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003, |
| 1009 | PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013, |
| 1010 | PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, |
| 1011 | PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, |
| 1012 | |
| 1013 | /* Config Base and Limit i Registers |
| 1014 | * F1:0xE0 i = 0 |
| 1015 | * F1:0xE4 i = 1 |
| 1016 | * F1:0xE8 i = 2 |
| 1017 | * F1:0xEC i = 3 |
| 1018 | * [ 0: 0] Read Enable |
| 1019 | * 0 = Reads Disabled |
| 1020 | * 1 = Reads Enabled |
| 1021 | * [ 1: 1] Write Enable |
| 1022 | * 0 = Writes Disabled |
| 1023 | * 1 = Writes Enabled |
| 1024 | * [ 2: 2] Device Number Compare Enable |
| 1025 | * 0 = The ranges are based on bus number |
| 1026 | * 1 = The ranges are ranges of devices on bus 0 |
| 1027 | * [ 3: 3] Reserved |
| 1028 | * [ 6: 4] Destination Node |
| 1029 | * 000 = Node 0 |
| 1030 | * 001 = Node 1 |
| 1031 | * 010 = Node 2 |
| 1032 | * 011 = Node 3 |
| 1033 | * 100 = Node 4 |
| 1034 | * 101 = Node 5 |
| 1035 | * 110 = Node 6 |
| 1036 | * 111 = Node 7 |
| 1037 | * [ 7: 7] Reserved |
| 1038 | * [ 9: 8] Destination Link |
| 1039 | * 00 = Link 0 |
| 1040 | * 01 = Link 1 |
| 1041 | * 10 = Link 2 |
| 1042 | * 11 - Reserved |
| 1043 | * [15:10] Reserved |
| 1044 | * [23:16] Bus Number Base i |
| 1045 | * This field defines the lowest bus number in configuration region i |
| 1046 | * [31:24] Bus Number Limit i |
| 1047 | * This field defines the highest bus number in configuration regin i |
| 1048 | */ |
| 1049 | PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, |
| 1050 | PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, |
| 1051 | PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, |
| 1052 | PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, |
| 1053 | #endif |
| 1054 | }; |
| 1055 | int i; |
| 1056 | int max; |
| 1057 | print_debug("setting up coherent ht domain....\r\n"); |
| 1058 | max = sizeof(register_values)/sizeof(register_values[0]); |
| 1059 | for(i = 0; i < max; i += 3) { |
| 1060 | unsigned long reg; |
| 1061 | #if 1 |
| 1062 | print_debug_hex32(register_values[i]); |
| 1063 | print_debug(" <-"); |
| 1064 | print_debug_hex32(register_values[i+2]); |
| 1065 | print_debug("\r\n"); |
| 1066 | #endif |
| 1067 | #if 0 |
| 1068 | reg = pci_read_config32(register_values[i]); |
| 1069 | reg &= register_values[i+1]; |
| 1070 | reg |= register_values[i+2] & ~register_values[i+1]; |
| 1071 | pci_write_config32(register_values[i], reg); |
| 1072 | #endif |
| 1073 | } |
| 1074 | print_debug("done.\r\n"); |
| 1075 | } |
| 1076 | |
| 1077 | static void main(void) |
| 1078 | { |
| 1079 | static const char msg[] = "hello world\r\n"; |
| 1080 | #if 0 |
| 1081 | write(STDOUT_FILENO, msg, sizeof(msg)); |
| 1082 | #endif |
| 1083 | #if 1 |
| 1084 | setup_coherent_ht_domain(); |
| 1085 | #endif |
| 1086 | _exit(0); |
| 1087 | } |