Edward O'Callaghan | 32960e3 | 2014-11-23 17:38:52 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/cpu.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <arch/ioapic.h> |
| 23 | #include <arch/smp/mpspec.h> |
| 24 | #include <console/console.h> |
| 25 | #include <cpu/amd/amdfam15.h> |
| 26 | #include <cpu/x86/lapic.h> |
| 27 | #include <device/pci.h> |
| 28 | #include <stdint.h> |
| 29 | #include <string.h> |
| 30 | #include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */ |
| 31 | |
| 32 | |
| 33 | u8 picr_data[0x54] = { |
| 34 | 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 35 | 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 36 | 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 37 | 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 38 | 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 39 | 0x1F,0x1F,0x1F,0x1F |
| 40 | }; |
| 41 | u8 intr_data[0x54] = { |
| 42 | 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 43 | 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 44 | 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 45 | 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 46 | 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 47 | 0x10,0x11,0x12,0x13 |
| 48 | }; |
| 49 | |
| 50 | static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) |
| 51 | { |
| 52 | mc->mpc_length += length; |
| 53 | mc->mpc_entry_count++; |
| 54 | } |
| 55 | |
| 56 | static void my_smp_write_bus(struct mp_config_table *mc, |
| 57 | unsigned char id, const char *bustype) |
| 58 | { |
| 59 | struct mpc_config_bus *mpc; |
| 60 | mpc = smp_next_mpc_entry(mc); |
| 61 | memset(mpc, '\0', sizeof(*mpc)); |
| 62 | mpc->mpc_type = MP_BUS; |
| 63 | mpc->mpc_busid = id; |
| 64 | memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); |
| 65 | smp_add_mpc_entry(mc, sizeof(*mpc)); |
| 66 | } |
| 67 | |
| 68 | static void *smp_write_config_table(void *v) |
| 69 | { |
| 70 | struct mp_config_table *mc; |
| 71 | int bus_isa; |
| 72 | u8 byte; |
| 73 | |
| 74 | /* |
| 75 | * By the time this function gets called, the IOAPIC registers |
| 76 | * have been written so they can be read to get the correct |
| 77 | * APIC ID and Version |
| 78 | */ |
| 79 | u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); |
| 80 | u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); |
| 81 | |
| 82 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 83 | |
| 84 | mptable_init(mc, LOCAL_APIC_ADDR); |
| 85 | memcpy(mc->mpc_oem, "AMD ", 8); |
| 86 | |
| 87 | smp_write_processors(mc); |
| 88 | |
| 89 | //mptable_write_buses(mc, NULL, &bus_isa); |
| 90 | my_smp_write_bus(mc, 0, "PCI "); |
| 91 | my_smp_write_bus(mc, 1, "PCI "); |
| 92 | bus_isa = 0x02; |
| 93 | my_smp_write_bus(mc, bus_isa, "ISA "); |
| 94 | |
| 95 | /* I/O APICs: APIC ID Version State Address */ |
| 96 | smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); |
| 97 | |
| 98 | /* PIC IRQ routine */ |
| 99 | for (byte = 0x0; byte < sizeof(picr_data); byte ++) { |
| 100 | outb(byte, 0xC00); |
| 101 | outb(picr_data[byte], 0xC01); |
| 102 | } |
| 103 | |
| 104 | /* APIC IRQ routine */ |
| 105 | for (byte = 0x0; byte < sizeof(intr_data); byte ++) { |
| 106 | outb(byte | 0x80, 0xC00); |
| 107 | outb(intr_data[byte], 0xC01); |
| 108 | } |
| 109 | |
| 110 | /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 111 | #define IO_LOCAL_INT(type, intr, apicid, pin) \ |
| 112 | smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); |
| 113 | mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); |
| 114 | |
| 115 | /* PCI interrupts are level triggered, and are |
| 116 | * associated with a specific bus/device/function tuple. |
| 117 | */ |
| 118 | #define PCI_INT(bus, dev, int_sign, pin) \ |
| 119 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) |
| 120 | |
Edward O'Callaghan | 14581fc6 | 2014-12-05 04:25:44 +1100 | [diff] [blame^] | 121 | /* IOMMU */ |
| 122 | PCI_INT(0x0, 0x00, 0x0, 0x10); |
| 123 | PCI_INT(0x0, 0x00, 0x1, 0x11); |
| 124 | PCI_INT(0x0, 0x00, 0x2, 0x12); |
| 125 | PCI_INT(0x0, 0x00, 0x3, 0x13); |
| 126 | |
Edward O'Callaghan | 32960e3 | 2014-11-23 17:38:52 +1100 | [diff] [blame] | 127 | /* Internal VGA */ |
| 128 | PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); |
| 129 | PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); |
| 130 | |
| 131 | /* SMBUS */ |
| 132 | PCI_INT(0x0, 0x14, 0x0, 0x10); |
| 133 | |
| 134 | /* HD Audio */ |
| 135 | PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); |
| 136 | |
| 137 | /* USB */ |
| 138 | PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); |
| 139 | PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); |
| 140 | PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); |
| 141 | PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); |
| 142 | PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); |
| 143 | PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); |
| 144 | PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); |
| 145 | |
| 146 | /* sata */ |
| 147 | PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); |
| 148 | PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); |
| 149 | |
| 150 | /* on board NIC & Slot PCIE. */ |
| 151 | |
| 152 | /* PCI slots */ |
| 153 | device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); |
| 154 | if (dev && dev->enabled) { |
| 155 | u8 bus_pci = dev->link_list->secondary; |
| 156 | /* PCI_SLOT 0. */ |
| 157 | PCI_INT(bus_pci, 0x5, 0x0, 0x14); |
| 158 | PCI_INT(bus_pci, 0x5, 0x1, 0x15); |
| 159 | PCI_INT(bus_pci, 0x5, 0x2, 0x16); |
| 160 | PCI_INT(bus_pci, 0x5, 0x3, 0x17); |
| 161 | |
| 162 | /* PCI_SLOT 1. */ |
| 163 | PCI_INT(bus_pci, 0x6, 0x0, 0x15); |
| 164 | PCI_INT(bus_pci, 0x6, 0x1, 0x16); |
| 165 | PCI_INT(bus_pci, 0x6, 0x2, 0x17); |
| 166 | PCI_INT(bus_pci, 0x6, 0x3, 0x14); |
| 167 | |
| 168 | /* PCI_SLOT 2. */ |
| 169 | PCI_INT(bus_pci, 0x7, 0x0, 0x16); |
| 170 | PCI_INT(bus_pci, 0x7, 0x1, 0x17); |
| 171 | PCI_INT(bus_pci, 0x7, 0x2, 0x14); |
| 172 | PCI_INT(bus_pci, 0x7, 0x3, 0x15); |
| 173 | } |
| 174 | |
| 175 | /* PCIe Lan*/ |
| 176 | PCI_INT(0x0, 0x06, 0x0, 0x13); |
| 177 | |
| 178 | /* FCH PCIe PortA */ |
| 179 | PCI_INT(0x0, 0x15, 0x0, 0x10); |
| 180 | /* FCH PCIe PortB */ |
| 181 | PCI_INT(0x0, 0x15, 0x1, 0x11); |
| 182 | /* FCH PCIe PortC */ |
| 183 | PCI_INT(0x0, 0x15, 0x2, 0x12); |
| 184 | /* FCH PCIe PortD */ |
| 185 | PCI_INT(0x0, 0x15, 0x3, 0x13); |
| 186 | |
| 187 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 188 | IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); |
| 189 | IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); |
| 190 | /* There is no extension information... */ |
| 191 | |
| 192 | /* Compute the checksums */ |
| 193 | return mptable_finalize(mc); |
| 194 | } |
| 195 | |
| 196 | unsigned long write_smp_table(unsigned long addr) |
| 197 | { |
| 198 | void *v; |
| 199 | v = smp_write_floating_table(addr, 0); |
| 200 | return (unsigned long)smp_write_config_table(v); |
| 201 | } |