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Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -05001/*
Martin Rothebace9f2018-05-26 18:56:17 -06002 * This file is part of the coreboot project.
Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -05003 *
4 * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Martin Rothebace9f2018-05-26 18:56:17 -06005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17/*
18 * Utilities for SMI handlers and SMM setup
Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -050019 */
20
21#ifndef _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H
22#define _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H
23
Kyösti Mälkki13f66502019-03-03 08:01:05 +020024#include <device/mmio.h>
Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -050025
26/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it.
27 * This is defined by AGESA, but we dpn't include AGESA headers to avoid
28 * polluting the namesace.
29 */
30#define SMI_BASE 0xfed80200
31
32#define SMI_REG_SMITRIG0 0x98
33#define SMITRG0_EOS (1 << 28)
34#define SMITRG0_SMIENB (1 << 31)
35
36#define SMI_REG_CONTROL0 0xa0
37
Alexandru Gagniuc599d6682014-04-17 23:33:50 -050038enum smi_mode {
39 SMI_MODE_DISABLE = 0,
40 SMI_MODE_SMI = 1,
41 SMI_MODE_NMI = 2,
42 SMI_MODE_IRQ13 = 3,
43};
44
45enum smi_lvl {
46 SMI_LVL_LOW = 0,
47 SMI_LVL_HIGH = 1,
Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -050048};
49
50static inline uint32_t smi_read32(uint8_t offset)
51{
Stefan Reinauer772029f2015-07-30 16:23:50 -070052 return read32((void *)((uintptr_t)SMI_BASE + offset));
Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -050053}
54
55static inline void smi_write32(uint8_t offset, uint32_t value)
56{
Stefan Reinauer772029f2015-07-30 16:23:50 -070057 write32((void *)((uintptr_t)SMI_BASE + offset), value);
Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -050058}
59
60static inline uint16_t smi_read16(uint8_t offset)
61{
Stefan Reinauer772029f2015-07-30 16:23:50 -070062 return read16((void *)((uintptr_t)SMI_BASE + offset));
Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -050063}
64
65static inline void smi_write16(uint8_t offset, uint16_t value)
66{
Stefan Reinauer772029f2015-07-30 16:23:50 -070067 write16((void *)((uintptr_t)SMI_BASE + offset), value);
Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -050068}
69
Alexandru Gagniuc599d6682014-04-17 23:33:50 -050070void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
71void hudson_disable_gevent_smi(uint8_t gevent);
72void hudson_enable_acpi_cmd_smi(void);
73
Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -050074#ifndef __SMM__
75void hudson_enable_smi_generation(void);
Alexandru Gagniuc2dbd08f2014-04-10 14:35:59 -050076#endif
77
78#endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */