Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * Copyright (C) 2017 Intel Corporation. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame^] | 18 | #include <device/mmio.h> |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 19 | #include <bootstate.h> |
| 20 | #include <chip.h> |
| 21 | #include <console/console.h> |
| 22 | #include <console/post_codes.h> |
| 23 | #include <cpu/x86/smm.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <intelblocks/lpc_lib.h> |
| 26 | #include <intelblocks/pcr.h> |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 27 | #include <intelblocks/tco.h> |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 28 | #include <reg_script.h> |
| 29 | #include <spi-generic.h> |
| 30 | #include <soc/p2sb.h> |
| 31 | #include <soc/pci_devs.h> |
| 32 | #include <soc/pcr_ids.h> |
| 33 | #include <soc/pm.h> |
| 34 | #include <soc/smbus.h> |
| 35 | #include <soc/systemagent.h> |
| 36 | #include <stdlib.h> |
| 37 | |
Lijian Zhao | 1b64ae1 | 2018-01-22 20:08:15 -0800 | [diff] [blame] | 38 | #define CAMERA1_CLK 0x8000 /* Camera 1 Clock */ |
| 39 | #define CAMERA2_CLK 0x8080 /* Camera 2 Clock */ |
| 40 | #define CAM_CLK_EN (1 << 1) |
| 41 | #define MIPI_CLK (1 << 0) |
| 42 | #define HDPLL_CLK (0 << 0) |
| 43 | |
Lijian Zhao | 1b64ae1 | 2018-01-22 20:08:15 -0800 | [diff] [blame] | 44 | static void pch_enable_isclk(void) |
| 45 | { |
| 46 | pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); |
| 47 | pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK); |
| 48 | } |
| 49 | |
| 50 | static void pch_handle_sideband(config_t *config) |
| 51 | { |
Lijian Zhao | 1b64ae1 | 2018-01-22 20:08:15 -0800 | [diff] [blame] | 52 | if (config->pch_isclk) |
| 53 | pch_enable_isclk(); |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 54 | } |
| 55 | |
| 56 | static void pch_finalize(void) |
| 57 | { |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 58 | struct device *dev; |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 59 | uint32_t reg32; |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 60 | uint8_t *pmcbase; |
| 61 | config_t *config; |
| 62 | uint8_t reg8; |
| 63 | |
Subrata Banik | 7bc4dc5 | 2018-05-17 18:40:32 +0530 | [diff] [blame] | 64 | tco_lockdown(); |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 65 | /* |
| 66 | * Disable ACPI PM timer based on dt policy |
| 67 | * |
| 68 | * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. |
| 69 | * Disabling ACPI PM timer also switches off TCO |
| 70 | */ |
| 71 | dev = PCH_DEV_PMC; |
| 72 | config = dev->chip_info; |
| 73 | pmcbase = pmc_mmio_regs(); |
| 74 | if (config->PmTimerDisabled) { |
| 75 | reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); |
| 76 | reg8 |= (1 << 1); |
| 77 | write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); |
| 78 | } |
| 79 | |
| 80 | /* Disable XTAL shutdown qualification for low power idle. */ |
| 81 | if (config->s0ix_enable) { |
| 82 | reg32 = read32(pmcbase + CPPMVRIC); |
| 83 | reg32 |= XTALSDQDIS; |
| 84 | write32(pmcbase + CPPMVRIC, reg32); |
| 85 | } |
| 86 | |
Lijian Zhao | 1b64ae1 | 2018-01-22 20:08:15 -0800 | [diff] [blame] | 87 | pch_handle_sideband(config); |
Lijian Zhao | 6cf501c | 2017-10-10 18:26:18 -0700 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | static void soc_finalize(void *unused) |
| 91 | { |
| 92 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
| 93 | |
| 94 | pch_finalize(); |
| 95 | |
| 96 | printk(BIOS_DEBUG, "Finalizing SMM.\n"); |
| 97 | outb(APM_CNT_FINALIZE, APM_CNT); |
| 98 | |
| 99 | /* Indicate finalize step with post code */ |
| 100 | post_code(POST_OS_BOOT); |
| 101 | } |
| 102 | |
| 103 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL); |
| 104 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL); |