| Matt DeVillier | 57e37c5 | 2020-05-01 12:53:31 -0500 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| Matt DeVillier | 8437ac5 | 2020-07-15 16:09:57 -0500 | [diff] [blame] | 3 | # Disable CLKREQ# for RP9 |
| 4 | register "PcieRpClkReqSupport[8]" = "0" |
| Matt DeVillier | 57e37c5 | 2020-05-01 12:53:31 -0500 | [diff] [blame] | 5 | # SRCCLKREQ2# for NVMe per schematic |
| 6 | register "PcieRpClkReqNumber[8]" = "2" |
| 7 | |
| 8 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port |
| 9 | register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) |
| 10 | register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right) |
| 11 | register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) |
| 12 | register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left) |
| 13 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 14 | register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |
| 15 | register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD |
| 16 | |
| 17 | # OC0 should be for Type-C but it seems to not have been wired, according to |
| 18 | # the available schematics, even though it is labeled as USB_OC_TYPEC. |
| 19 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port |
| 20 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) |
| 21 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right) |
| 22 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port |
| 23 | |
| 24 | device domain 0 on |
| Felix Singer | 13ee2e6 | 2023-11-12 18:29:57 +0000 | [diff] [blame^] | 25 | device ref pcie_rp5 on end |
| Matt DeVillier | 57e37c5 | 2020-05-01 12:53:31 -0500 | [diff] [blame] | 26 | end |
| 27 | end |