Tim Chu | 13c4445 | 2022-11-25 10:31:00 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <device/pci_ops.h> |
| 4 | #include <soc/pci_devs.h> |
| 5 | #include <soc/pcr_ids.h> |
| 6 | #include <intelblocks/pcr.h> |
| 7 | #include <intelblocks/rtc.h> |
| 8 | #include <intelblocks/p2sb.h> |
| 9 | #include <soc/bootblock.h> |
| 10 | #include <soc/soc_pch.h> |
| 11 | #include <soc/pmc.h> |
| 12 | #include <console/console.h> |
| 13 | |
| 14 | #define PCR_DMI_ACPIBA 0x27B4 |
| 15 | #define PCR_DMI_ACPIBDID 0x27B8 |
| 16 | #define PCR_DMI_DMICTL 0x2234 |
| 17 | #define PCR_DMI_DMICTL_SRLOCK (1 << 31) |
| 18 | #define PCR_DMI_PMBASEA 0x27AC |
| 19 | #define PCR_DMI_PMBASEC 0x27B0 |
| 20 | |
| 21 | static void soc_config_acpibase(void) |
| 22 | { |
| 23 | uint32_t reg32; |
| 24 | |
| 25 | /* Disable ABASE in PMC Device first before changing Base Address */ |
| 26 | reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); |
| 27 | pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); |
| 28 | |
| 29 | /* Program ACPI Base */ |
| 30 | pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); |
| 31 | |
| 32 | /* Enable ACPI in PMC */ |
| 33 | pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); |
| 34 | |
| 35 | uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE); |
| 36 | printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data); |
| 37 | /* |
| 38 | * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] |
| 39 | * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] |
| 40 | */ |
| 41 | reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; |
| 42 | pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); |
| 43 | pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); |
| 44 | } |
| 45 | |
| 46 | void bootblock_pch_init(void) |
| 47 | { |
| 48 | /* |
| 49 | * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT |
| 50 | */ |
| 51 | soc_config_acpibase(); |
| 52 | } |
| 53 | |
| 54 | void pch_lock_dmictl(void) |
| 55 | { |
| 56 | uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); |
| 57 | pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); |
| 58 | } |