blob: c3e716527a080b90b3872b5dada1b7b4fc200a86 [file] [log] [blame]
Patrick Georgiac959032020-05-05 22:49:26 +02001/* SPDX-License-Identifier: GPL-2.0-or-later */
Jonathan Zhang75985f12020-01-16 11:20:09 -08002
3#include <fsp/api.h>
4#include <FspmUpd.h>
Sergii Dmytrukef7dd5d2021-10-22 01:02:32 +03005#include <drivers/ipmi/ipmi_if.h>
Johnny Lin3acea5c2021-01-08 15:24:25 +08006#include <drivers/ipmi/ocp/ipmi_ocp.h>
Jonathan Zhang75985f12020-01-16 11:20:09 -08007#include <soc/romstage.h>
Johnny Lin3b9d9952020-03-27 22:06:30 +08008#include <string.h>
9#include <gpio.h>
Tim Chu13c44452022-11-25 10:31:00 +000010#include <soc/gpio_soc_defs.h>
Maxim Polyakov8fb221d2020-04-26 20:56:50 +030011#include <skxsp_tp_iio.h>
Jonathan Zhang75985f12020-01-16 11:20:09 -080012
Johnny Lindcc2eb92020-01-14 09:17:18 +080013#include "ipmi.h"
14
Johnny Lin3b9d9952020-03-27 22:06:30 +080015static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)];
16
17static void oem_update_iio(FSPM_UPD *mupd)
18{
19 /* Read GPIO to decide IIO bifurcation at run-time. */
20 int slot_config0 = gpio_get(GPP_C15);
21 int slot_config1 = gpio_get(GPP_C16);
22
23 /* It's a single side 3 slots riser card, to tell which AICs are on each slot requires
24 reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation
25 accordingly is left for future work. */
26 if (!slot_config0 && slot_config1)
27 mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation
28 = IIO_BIFURCATE_xxx8xxx8;
29}
30
Jonathan Zhang75985f12020-01-16 11:20:09 -080031static void mainboard_config_iio(FSPM_UPD *mupd)
32{
Johnny Lin3b9d9952020-03-27 22:06:30 +080033 memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table));
Jonathan Zhang75985f12020-01-16 11:20:09 -080034 mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable =
Johnny Lin3b9d9952020-03-27 22:06:30 +080035 (UPD_IIO_BIFURCATION_DATA_ENTRY *) iio_table_buf;
Jonathan Zhang75985f12020-01-16 11:20:09 -080036 mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries =
37 ARRAY_SIZE(tp_iio_bifur_table);
38
39 mupd->FspmConfig.IioPciConfig.ConfigurationTable =
40 (UPD_PCI_PORT_CONFIG *) tp_iio_pci_port_skt0;
41 mupd->FspmConfig.IioPciConfig.NumberOfEntries =
42 ARRAY_SIZE(tp_iio_pci_port_skt0);
43
44 mupd->FspmConfig.PchPciConfig.PciPortConfig =
45 (UPD_PCH_PCIE_PORT *) tp_pch_pci_port_skt0;
46 mupd->FspmConfig.PchPciConfig.NumberOfEntries =
47 ARRAY_SIZE(tp_pch_pci_port_skt0);
48
49 mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00;
50 mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00;
Johnny Lin3b9d9952020-03-27 22:06:30 +080051 oem_update_iio(mupd);
Jonathan Zhang75985f12020-01-16 11:20:09 -080052}
53
54void mainboard_memory_init_params(FSPM_UPD *mupd)
55{
Johnny Lindcc2eb92020-01-14 09:17:18 +080056 /* It's better to run get BMC selftest result first */
Sergii Dmytrukef7dd5d2021-10-22 01:02:32 +030057 if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) {
Johnny Lin3acea5c2021-01-08 15:24:25 +080058 ipmi_set_post_start(CONFIG_BMC_KCS_BASE);
Johnny Lindcc2eb92020-01-14 09:17:18 +080059 init_frb2_wdt();
Johnny Lin3acea5c2021-01-08 15:24:25 +080060 }
Jonathan Zhang75985f12020-01-16 11:20:09 -080061 mainboard_config_iio(mupd);
Maxim Polyakov89d2aa02020-04-26 20:56:50 +030062
63 /* do not configure GPIO controller inside FSP-M */
64 mupd->FspmConfig.GpioConfig.GpioTable = NULL;
65 mupd->FspmConfig.GpioConfig.NumberOfEntries = 0;
Jonathan Zhang75985f12020-01-16 11:20:09 -080066}