blob: 707e48b5040ea0a335a6d66f8600865a11e02999 [file] [log] [blame]
Frans Hendriks43b6e2e2019-06-04 13:53:05 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 Google Inc.
6 * Copyright (C) 2015-2018 Intel Corp.
7 * Copyright (C) 2018 Eltan B.V.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <arch/acpi.h>
20
Frans Hendriksc1c53542019-12-06 16:04:50 +010021#define SDCARD_CD 81 /* Not used */
22
Frans Hendriks43b6e2e2019-06-04 13:53:05 +020023DefinitionBlock(
24 "dsdt.aml",
25 "DSDT",
26 0x02, /* DSDT revision: ACPI v2.0 and up */
27 OEM_ID,
28 ACPI_TABLE_CREATOR,
29 0x20110725 /* OEM revision */
30)
31{
Frans Hendriks43b6e2e2019-06-04 13:53:05 +020032 #include <acpi/platform.asl>
33
34 /* global NVS and variables */
35 #include <acpi/globalnvs.asl>
36
37 #include <cpu/intel/common/acpi/cpu.asl>
38
39 Scope (\_SB) {
40 Device (PCI0)
41 {
42 #include <acpi/southcluster.asl>
43 }
44 }
45
Wim Vervoorn13471bc2020-01-16 10:28:14 +010046 #include <southbridge/intel/common/acpi/sleepstates.asl>
47
48 /* Mainboard specific */
Frans Hendriks43b6e2e2019-06-04 13:53:05 +020049 #include "acpi/mainboard.asl"
50}