Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * 2012 secunet Security Networks AG |
| 6 | * (Written by Nico Huber <nico.huber@secunet.com> for secunet) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; version 2 of |
| 11 | * the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <stdlib.h> |
| 20 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 21 | #include <device/pci_ops.h> |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <console/console.h> |
| 25 | #include "i82801ix.h" |
| 26 | |
| 27 | typedef struct southbridge_intel_i82801ix_config config_t; |
| 28 | |
Elyes HAOUAS | 8aa5073 | 2018-05-13 13:34:58 +0200 | [diff] [blame] | 29 | static void i82801ix_enable_device(struct device *dev) |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 30 | { |
| 31 | u32 reg32; |
| 32 | |
| 33 | /* Enable SERR */ |
| 34 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 35 | reg32 |= PCI_COMMAND_SERR; |
| 36 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 37 | } |
| 38 | |
| 39 | static void i82801ix_early_settings(const config_t *const info) |
| 40 | { |
| 41 | /* Program FERR# as processor break event indicator. */ |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 42 | RCBA32(GCS) |= (1 << 6); |
| 43 | /* BIOS must program... |
| 44 | * NB: other CIRs are handled in i82801ix_dmi_setup(). */ |
| 45 | RCBA32(RCBA_CIR8) = (RCBA32(RCBA_CIR8) & ~(0x3 << 0)) | (0x2 << 0); |
| 46 | RCBA32(RCBA_FD) |= (1 << 0); |
| 47 | RCBA32(RCBA_CIR9) = (RCBA32(RCBA_CIR9) & ~(0x3 << 26)) | (0x2 << 26); |
| 48 | RCBA32(RCBA_CIR7) = (RCBA32(RCBA_CIR7) & ~(0xf << 16)) | (0x5 << 16); |
| 49 | RCBA32(RCBA_CIR13) = (RCBA32(RCBA_CIR13) & ~(0xf << 16)) | (0x5 << 16); |
Stefan Tauner | 97c8089 | 2018-08-15 08:06:13 +0200 | [diff] [blame] | 50 | /* RCBA32(RCBA_CIR5) |= (1 << 0); cf. Specification Update */ |
Stefan Tauner | cea31ea | 2018-08-11 18:45:28 +0200 | [diff] [blame] | 51 | RCBA32(RCBA_CIR10) |= (3 << 16); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | static void i82801ix_pcie_init(const config_t *const info) |
| 55 | { |
Elyes HAOUAS | 8aa5073 | 2018-05-13 13:34:58 +0200 | [diff] [blame] | 56 | struct device *pciePort[6]; |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 57 | int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */ |
| 58 | u32 reg32; |
| 59 | |
| 60 | /* PCIe - BIOS must program... */ |
| 61 | for (i = 0; i < 6; ++i) { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 62 | pciePort[i] = pcidev_on_root(0x1c, i); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 63 | if (!pciePort[i]) { |
| 64 | printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); |
| 65 | die(" is not listed in devicetree.\n"); |
| 66 | } |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame] | 67 | reg32 = pci_read_config32(pciePort[i], 0x300); |
| 68 | pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); |
| 69 | pci_write_config8(pciePort[i], 0x324, 0x40); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 70 | } |
| 71 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 72 | if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) { |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 73 | for (i = 0; i < 6; ++i) { |
| 74 | if (pciePort[i]->enabled) { |
| 75 | reg32 = pci_read_config32(pciePort[i], 0xe8); |
| 76 | reg32 |= 1; |
| 77 | pci_write_config32(pciePort[i], 0xe8, reg32); |
| 78 | } |
| 79 | } |
| 80 | } |
| 81 | |
| 82 | for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { |
| 83 | /* Only for the top disabled ports. */ |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame] | 84 | reg32 = pci_read_config32(pciePort[i], 0x300); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 85 | reg32 |= 0x3 << 16; |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame] | 86 | pci_write_config32(pciePort[i], 0x300, reg32); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 87 | } |
| 88 | |
| 89 | /* Set slot implemented, slot number and slot power limits. */ |
| 90 | for (i = 0; i < 6; ++i) { |
Elyes HAOUAS | 8aa5073 | 2018-05-13 13:34:58 +0200 | [diff] [blame] | 91 | struct device *const dev = pciePort[i]; |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 92 | u32 xcap = pci_read_config32(dev, D28Fx_XCAP); |
| 93 | if (info->pcie_slot_implemented & (1 << i)) |
| 94 | xcap |= PCI_EXP_FLAGS_SLOT; |
| 95 | else |
| 96 | xcap &= ~PCI_EXP_FLAGS_SLOT; |
| 97 | pci_write_config32(dev, D28Fx_XCAP, xcap); |
| 98 | |
| 99 | if (info->pcie_slot_implemented & (1 << i)) { |
| 100 | u32 slcap = pci_read_config32(dev, D28Fx_SLCAP); |
| 101 | slcap &= ~(0x1fff << 19); |
| 102 | slcap |= (slot_number++ << 19); |
| 103 | slcap &= ~(0x0003 << 16); |
| 104 | slcap |= (info->pcie_power_limits[i].scale << 16); |
| 105 | slcap &= ~(0x00ff << 7); |
| 106 | slcap |= (info->pcie_power_limits[i].value << 7); |
| 107 | pci_write_config32(dev, D28Fx_SLCAP, slcap); |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | /* Lock R/WO ASPM support bits. */ |
| 112 | for (i = 0; i < 6; ++i) { |
| 113 | reg32 = pci_read_config32(pciePort[i], 0x4c); |
| 114 | pci_write_config32(pciePort[i], 0x4c, reg32); |
| 115 | } |
| 116 | } |
| 117 | |
| 118 | static void i82801ix_ehci_init(void) |
| 119 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 120 | struct device *const pciEHCI1 = pcidev_on_root(0x1d, 7); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 121 | if (!pciEHCI1) |
| 122 | die("EHCI controller (00:1d.7) not listed in devicetree.\n"); |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 123 | struct device *const pciEHCI2 = pcidev_on_root(0x1a, 7); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 124 | if (!pciEHCI2) |
| 125 | die("EHCI controller (00:1a.7) not listed in devicetree.\n"); |
| 126 | |
| 127 | u32 reg32; |
| 128 | |
| 129 | /* TODO: Maybe we have to save and |
| 130 | restore these settings across S3. */ |
| 131 | reg32 = pci_read_config32(pciEHCI1, 0xfc); |
| 132 | pci_write_config32(pciEHCI1, 0xfc, (reg32 & ~(3 << 2)) | |
| 133 | (1 << 29) | (1 << 17) | (2 << 2)); |
| 134 | reg32 = pci_read_config32(pciEHCI2, 0xfc); |
| 135 | pci_write_config32(pciEHCI2, 0xfc, (reg32 & ~(3 << 2)) | |
| 136 | (1 << 29) | (1 << 17) | (2 << 2)); |
| 137 | } |
| 138 | |
| 139 | static int i82801ix_function_disabled(const unsigned devfn) |
| 140 | { |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 141 | struct device *const dev = pcidev_path_on_root(devfn); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 142 | if (!dev) { |
| 143 | printk(BIOS_EMERG, |
| 144 | "PCI device 00:%x.%x", |
| 145 | PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 146 | die(" is not listed in devicetree.\n"); |
| 147 | } |
| 148 | return !dev->enabled; |
| 149 | } |
| 150 | |
| 151 | static void i82801ix_hide_functions(void) |
| 152 | { |
| 153 | int i; |
| 154 | u32 reg32; |
| 155 | |
| 156 | /* FIXME: This works pretty good if the devicetree is consistent. But |
| 157 | some functions have to be disabled in right order and/or have |
| 158 | other constraints. */ |
| 159 | |
| 160 | if (i82801ix_function_disabled(PCI_DEVFN(0x19, 0))) |
| 161 | RCBA32(RCBA_BUC) |= BUC_LAND; |
| 162 | |
| 163 | reg32 = RCBA32(RCBA_FD); |
| 164 | struct { |
| 165 | int devfn; |
| 166 | u32 mask; |
| 167 | } functions[] = { |
| 168 | { PCI_DEVFN(0x1a, 0), FD_U4D }, /* UHCI #4 */ |
| 169 | { PCI_DEVFN(0x1a, 1), FD_U5D }, /* UHCI #5 */ |
| 170 | { PCI_DEVFN(0x1a, 2), FD_U6D }, /* UHCI #6 */ |
| 171 | { PCI_DEVFN(0x1a, 7), FD_EHCI2D }, /* EHCI #2 */ |
| 172 | { PCI_DEVFN(0x1b, 0), FD_HDAD }, /* HD Audio */ |
| 173 | { PCI_DEVFN(0x1c, 0), FD_PE1D }, /* PCIe #1 */ |
| 174 | { PCI_DEVFN(0x1c, 1), FD_PE2D }, /* PCIe #2 */ |
| 175 | { PCI_DEVFN(0x1c, 2), FD_PE3D }, /* PCIe #3 */ |
| 176 | { PCI_DEVFN(0x1c, 3), FD_PE4D }, /* PCIe #4 */ |
| 177 | { PCI_DEVFN(0x1c, 4), FD_PE5D }, /* PCIe #5 */ |
| 178 | { PCI_DEVFN(0x1c, 5), FD_PE6D }, /* PCIe #6 */ |
| 179 | { PCI_DEVFN(0x1d, 0), FD_U1D }, /* UHCI #1 */ |
| 180 | { PCI_DEVFN(0x1d, 1), FD_U2D }, /* UHCI #2 */ |
| 181 | { PCI_DEVFN(0x1d, 2), FD_U3D }, /* UHCI #3 */ |
| 182 | { PCI_DEVFN(0x1d, 7), FD_EHCI1D }, /* EHCI #1 */ |
| 183 | { PCI_DEVFN(0x1f, 0), FD_LBD }, /* LPC */ |
| 184 | { PCI_DEVFN(0x1f, 2), FD_SAD1 }, /* SATA #1 */ |
| 185 | { PCI_DEVFN(0x1f, 3), FD_SD }, /* SMBus */ |
| 186 | { PCI_DEVFN(0x1f, 5), FD_SAD2 }, /* SATA #2 */ |
| 187 | { PCI_DEVFN(0x1f, 6), FD_TTD }, /* Thermal Throttle */ |
| 188 | }; |
| 189 | for (i = 0; i < ARRAY_SIZE(functions); ++i) { |
| 190 | if (i82801ix_function_disabled(functions[i].devfn)) |
| 191 | reg32 |= functions[i].mask; |
| 192 | } |
| 193 | RCBA32(RCBA_FD) = reg32; |
| 194 | RCBA32(RCBA_FD) |= (1 << 0); /* BIOS must write this... */ |
| 195 | RCBA32(RCBA_FDSW) |= (1 << 7); /* Lock function-disable? */ |
| 196 | |
| 197 | /* Hide PCIe root port PCI functions. RPFN is partially R/WO. */ |
| 198 | reg32 = RCBA32(RCBA_RPFN); |
| 199 | for (i = 0; i < 6; ++i) { |
| 200 | if (i82801ix_function_disabled(PCI_DEVFN(0x1c, i))) |
| 201 | reg32 |= (1 << ((i * 4) + 3)); |
| 202 | } |
| 203 | RCBA32(RCBA_RPFN) = reg32; |
| 204 | |
| 205 | /* Lock R/WO UHCI controller #6 remapping. */ |
| 206 | RCBA32(RCBA_MAP) = RCBA32(RCBA_MAP); |
| 207 | } |
| 208 | |
| 209 | static void i82801ix_init(void *chip_info) |
| 210 | { |
| 211 | const config_t *const info = (config_t *)chip_info; |
| 212 | |
| 213 | printk(BIOS_DEBUG, "Initializing i82801ix southbridge...\n"); |
| 214 | |
| 215 | i82801ix_early_settings(info); |
| 216 | |
| 217 | /* PCI Express setup. */ |
| 218 | i82801ix_pcie_init(info); |
| 219 | |
| 220 | /* EHCI configuration. */ |
| 221 | i82801ix_ehci_init(); |
| 222 | |
| 223 | /* Now hide internal functions. We can't access them after this. */ |
| 224 | i82801ix_hide_functions(); |
| 225 | |
| 226 | /* Reset watchdog timer. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 227 | #if !CONFIG(HAVE_SMI_HANDLER) |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 228 | outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ |
| 229 | #endif |
| 230 | outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | struct chip_operations southbridge_intel_i82801ix_ops = { |
| 234 | CHIP_NAME("Intel ICH9/ICH9-M (82801Ix) Series Southbridge") |
| 235 | .enable_dev = i82801ix_enable_device, |
| 236 | .init = i82801ix_init, |
| 237 | }; |