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Angel Pons4b429832020-04-02 23:48:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Duncan Laurie0a7c49e2013-06-20 12:40:55 -07002
3#include <console/console.h>
4#include <device/device.h>
5#include <device/pci.h>
6#include <device/pci_ids.h>
7#include <device/pci_ops.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +02008#include <device/mmio.h>
Duncan Laurie0a7c49e2013-06-20 12:40:55 -07009#include <southbridge/intel/lynxpoint/hda_verb.h>
10
11static const u32 minihd_verb_table[] = {
12 /* coreboot specific header */
Angel Pons1db5bc72020-01-15 00:49:03 +010013 0x80862807, /* Codec Vendor / Device ID: Intel Haswell Mini-HD */
14 0x80860101, /* Subsystem ID */
15 4, /* Number of jacks */
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070016
17 /* Enable 3rd Pin and Converter Widget */
18 0x00878101,
19
20 /* Pin Widget 5 - PORT B */
Angel Pons1db5bc72020-01-15 00:49:03 +010021 0x00571c10,
22 0x00571d00,
23 0x00571e56,
24 0x00571f18,
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070025
26 /* Pin Widget 6 - PORT C */
Angel Pons1db5bc72020-01-15 00:49:03 +010027 0x00671c20,
28 0x00671d00,
29 0x00671e56,
30 0x00671f18,
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070031
32 /* Pin Widget 7 - PORT D */
Angel Pons1db5bc72020-01-15 00:49:03 +010033 0x00771c30,
34 0x00771d00,
35 0x00771e56,
36 0x00771f18,
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070037
38 /* Disable 3rd Pin and Converter Widget */
39 0x00878100,
40
41 /* Dummy entries to fill out the table */
42 0x00878100,
43 0x00878100,
44};
45
46static void minihd_init(struct device *dev)
47{
48 struct resource *res;
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080049 u32 reg32;
50 u8 *base;
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070051 int codec_mask, i;
52
53 /* Find base address */
54 res = find_resource(dev, PCI_BASE_ADDRESS_0);
55 if (!res)
56 return;
57
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080058 base = res2mmio(res, 0, 0);
59 printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070060
61 /* Set Bus Master */
Angel Ponseb860162020-06-20 18:03:27 +020062 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070063
64 /* Mini-HD configuration */
65 reg32 = read32(base + 0x100c);
66 reg32 &= 0xfffc0000;
67 reg32 |= 0x4;
68 write32(base + 0x100c, reg32);
69
70 reg32 = read32(base + 0x1010);
71 reg32 &= 0xfffc0000;
72 reg32 |= 0x4b;
73 write32(base + 0x1010, reg32);
74
75 /* Init the codec and write the verb table */
76 codec_mask = hda_codec_detect(base);
77
78 if (codec_mask) {
79 for (i = 3; i >= 0; i--) {
80 if (codec_mask & (1 << i))
Angel Pons1db5bc72020-01-15 00:49:03 +010081 hda_codec_init(base, i, sizeof(minihd_verb_table),
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070082 minihd_verb_table);
83 }
84 }
85}
86
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070087static struct device_operations minihd_ops = {
88 .read_resources = pci_dev_read_resources,
89 .set_resources = pci_dev_set_resources,
90 .enable_resources = pci_dev_enable_resources,
91 .init = minihd_init,
Angel Pons1fc0edd2020-05-31 00:03:28 +020092 .ops_pci = &pci_dev_ops_pci,
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070093};
94
Iru Cai12a13e12020-05-22 22:57:03 +080095static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0x0d0c, 0 };
Duncan Laurie0a7c49e2013-06-20 12:40:55 -070096
97static const struct pci_driver haswell_minihd __pci_driver = {
98 .ops = &minihd_ops,
99 .vendor = PCI_VENDOR_ID_INTEL,
100 .devices = pci_device_ids,
101};