Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 1 | package main |
| 2 | |
| 3 | import ( |
| 4 | "fmt" |
| 5 | "os" |
| 6 | ) |
| 7 | |
| 8 | type bd82x6x struct { |
| 9 | variant string |
| 10 | node *DevTreeNode |
| 11 | } |
| 12 | |
| 13 | func (b bd82x6x) writeGPIOSet(ctx Context, sb *os.File, |
Arthur Heymans | 128205fd | 2017-05-01 09:40:43 +0200 | [diff] [blame^] | 14 | val uint32, set uint, partno int, constraint uint32) { |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 15 | |
| 16 | max := uint(32) |
| 17 | if set == 3 { |
| 18 | max = 12 |
| 19 | } |
| 20 | |
| 21 | bits := [6][2]string{ |
| 22 | {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, |
| 23 | {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, |
| 24 | {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, |
| 25 | {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, |
| 26 | {"GPIO_NO_INVERT", "GPIO_INVERT"}, |
| 27 | {"GPIO_NO_BLINK", "GPIO_BLINK"}, |
| 28 | } |
| 29 | |
| 30 | for i := uint(0); i < max; i++ { |
Arthur Heymans | 128205fd | 2017-05-01 09:40:43 +0200 | [diff] [blame^] | 31 | if ((constraint>>i)&1 == 1) { |
| 32 | fmt.Fprintf(sb, " .gpio%d = %s,\n", |
| 33 | (set-1)*32+i, |
| 34 | bits[partno][(val>>i)&1]) |
| 35 | } |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 36 | } |
| 37 | } |
| 38 | |
| 39 | func (b bd82x6x) GPIO(ctx Context, inteltool InteltoolData) { |
Arthur Heymans | 128205fd | 2017-05-01 09:40:43 +0200 | [diff] [blame^] | 40 | var constraint uint32 |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 41 | gpio := Create(ctx, "gpio.c") |
| 42 | defer gpio.Close() |
| 43 | |
| 44 | AddROMStageFile("gpio.c", "") |
| 45 | |
Arthur Heymans | 128205fd | 2017-05-01 09:40:43 +0200 | [diff] [blame^] | 46 | gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n") |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 47 | |
Arthur Heymans | 128205fd | 2017-05-01 09:40:43 +0200 | [diff] [blame^] | 48 | addresses := [3][6]int{ |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 49 | {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, |
| 50 | {0x30, 0x34, 0x38, 0x64, -1, -1}, |
| 51 | {0x40, 0x44, 0x48, 0x68, -1, -1}, |
| 52 | } |
| 53 | |
| 54 | for set := 1; set <= 3; set++ { |
| 55 | for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { |
Arthur Heymans | 128205fd | 2017-05-01 09:40:43 +0200 | [diff] [blame^] | 56 | addr := addresses[set-1][partno] |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 57 | if addr < 0 { |
| 58 | continue |
| 59 | } |
Arthur Heymans | 128205fd | 2017-05-01 09:40:43 +0200 | [diff] [blame^] | 60 | fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 61 | set, set, part) |
| 62 | |
Arthur Heymans | 128205fd | 2017-05-01 09:40:43 +0200 | [diff] [blame^] | 63 | constraint = 0xffffffff |
| 64 | switch part { |
| 65 | case "direction": |
| 66 | /* Ignored on native mode */ |
| 67 | constraint = inteltool.GPIO[uint16(addresses[set-1][0])] |
| 68 | case "level": |
| 69 | /* Level doesn't matter for input */ |
| 70 | constraint = inteltool.GPIO[uint16(addresses[set-1][0])] |
| 71 | constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] |
| 72 | case "reset": |
| 73 | /* Only show reset */ |
| 74 | constraint = inteltool.GPIO[uint16(addresses[set-1][3])] |
| 75 | case "invert": |
| 76 | /* Only on input and only show inverted GPIO */ |
| 77 | constraint = inteltool.GPIO[uint16(addresses[set-1][0])] |
| 78 | constraint &= inteltool.GPIO[uint16(addresses[set-1][1])] |
| 79 | constraint &= inteltool.GPIO[uint16(addresses[set-1][4])] |
| 80 | case "blink": |
| 81 | /* Only on output and only show blinking GPIO */ |
| 82 | constraint = inteltool.GPIO[uint16(addresses[set-1][0])] |
| 83 | constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] |
| 84 | constraint &= inteltool.GPIO[uint16(addresses[set-1][5])] |
| 85 | } |
| 86 | b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint) |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 87 | gpio.WriteString("};\n\n") |
| 88 | } |
| 89 | } |
| 90 | |
| 91 | gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = { |
| 92 | .set1 = { |
| 93 | .mode = &pch_gpio_set1_mode, |
| 94 | .direction = &pch_gpio_set1_direction, |
| 95 | .level = &pch_gpio_set1_level, |
| 96 | .blink = &pch_gpio_set1_blink, |
| 97 | .invert = &pch_gpio_set1_invert, |
| 98 | .reset = &pch_gpio_set1_reset, |
| 99 | }, |
| 100 | .set2 = { |
| 101 | .mode = &pch_gpio_set2_mode, |
| 102 | .direction = &pch_gpio_set2_direction, |
| 103 | .level = &pch_gpio_set2_level, |
| 104 | .reset = &pch_gpio_set2_reset, |
| 105 | }, |
| 106 | .set3 = { |
| 107 | .mode = &pch_gpio_set3_mode, |
| 108 | .direction = &pch_gpio_set3_direction, |
| 109 | .level = &pch_gpio_set3_level, |
| 110 | .reset = &pch_gpio_set3_reset, |
| 111 | }, |
| 112 | }; |
| 113 | `) |
| 114 | } |
| 115 | |
| 116 | func (b bd82x6x) IsPCIeHotplug(ctx Context, port int) bool { |
| 117 | portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}] |
| 118 | if !ok { |
| 119 | return false |
| 120 | } |
| 121 | return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 |
| 122 | } |
| 123 | |
| 124 | func ich9GetFlashSize(ctx Context) { |
| 125 | inteltool := ctx.InfoSource.GetInteltool() |
| 126 | switch (inteltool.RCBA[0x3410] >> 10) & 3 { |
| 127 | /* SPI. All boards I've seen with sandy/ivy use SPI. */ |
| 128 | case 3: |
| 129 | ROMProtocol = "SPI" |
| 130 | highflkb := uint32(0) |
| 131 | for reg := uint16(0); reg < 5; reg++ { |
| 132 | fl := (inteltool.RCBA[0x3854+4*reg] >> 16) & 0x1fff |
Vladimir Serbinenko | 68f5f62 | 2015-05-29 21:43:42 +0200 | [diff] [blame] | 133 | flkb := (fl + 1) << 2 |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 134 | if flkb > highflkb { |
| 135 | highflkb = flkb |
| 136 | } |
| 137 | } |
| 138 | ROMSizeKB = int(highflkb) |
| 139 | /* Shared with ME. Flashrom is unable to handle it. */ |
| 140 | FlashROMSupport = "n" |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | func (b bd82x6x) GetGPIOHeader() string { |
| 145 | return "southbridge/intel/bd82x6x/pch.h" |
| 146 | } |
| 147 | |
| 148 | func (b bd82x6x) EnableGPE(in int) { |
| 149 | b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2" |
| 150 | } |
| 151 | |
| 152 | func (b bd82x6x) EncodeGPE(in int) int { |
| 153 | return in + 0x10 |
| 154 | } |
| 155 | |
| 156 | func (b bd82x6x) DecodeGPE(in int) int { |
| 157 | return in - 0x10 |
| 158 | } |
| 159 | |
| 160 | func (b bd82x6x) NeedRouteGPIOManually() { |
| 161 | b.node.Comment += ", FIXME: set gpiX_routing for EC support" |
| 162 | } |
| 163 | |
| 164 | func (b bd82x6x) Scan(ctx Context, addr PCIDevData) { |
| 165 | |
| 166 | SouthBridge = &b |
| 167 | |
| 168 | inteltool := ctx.InfoSource.GetInteltool() |
| 169 | b.GPIO(ctx, inteltool) |
| 170 | |
| 171 | KconfigBool["SOUTHBRIDGE_INTEL_"+b.variant] = true |
| 172 | KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true |
| 173 | KconfigInt["USBDEBUG_HCD_INDEX"] = 2 |
| 174 | KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this" |
| 175 | dmi := ctx.InfoSource.GetDMI() |
| 176 | if dmi.Vendor == "LENOVO" { |
| 177 | KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 |
| 178 | } else { |
| 179 | KconfigInt["DRAM_RESET_GATE_GPIO"] = 60 |
| 180 | } |
| 181 | KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" |
| 182 | |
| 183 | /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices. |
| 184 | But most systems don't have any of those. But the config needs to be set |
| 185 | nevertheless. So set it to southbridge subsys/subvendor. */ |
| 186 | KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e])) |
| 187 | KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30])) |
| 188 | |
| 189 | ich9GetFlashSize(ctx) |
| 190 | |
| 191 | DSDTDefines = append(DSDTDefines, |
| 192 | DSDTDefine{ |
| 193 | Key: "BRIGHTNESS_UP", |
| 194 | Value: "\\_SB.PCI0.GFX0.INCB", |
| 195 | }, |
| 196 | DSDTDefine{ |
| 197 | Key: "BRIGHTNESS_DOWN", |
| 198 | Value: "\\_SB.PCI0.GFX0.DECB", |
| 199 | }, |
| 200 | DSDTDefine{ |
| 201 | Key: "ACPI_VIDEO_DEVICE", |
| 202 | Value: "\\_SB.PCI0.GFX0", |
| 203 | }) |
| 204 | |
| 205 | /* SPI init */ |
| 206 | MainboardIncludes = append(MainboardIncludes, "southbridge/intel/bd82x6x/pch.h") |
| 207 | /* FIXME:XX Move this to runtime. */ |
Patrick Rudolph | 0a4a4f7 | 2017-04-29 18:39:32 +0200 | [diff] [blame] | 208 | for _, addr := range []uint16{0x38c8, 0x38c4} { |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 209 | MainboardInit += fmt.Sprintf("\tRCBA32(0x%04x) = 0x%08x;\n", addr, inteltool.RCBA[addr]) |
| 210 | } |
| 211 | |
| 212 | FADT := ctx.InfoSource.GetACPI()["FACP"] |
| 213 | |
| 214 | pcieHotplugMap := "{ " |
| 215 | |
| 216 | for port := 0; port < 7; port++ { |
| 217 | if b.IsPCIeHotplug(ctx, port) { |
| 218 | pcieHotplugMap += "1, " |
| 219 | } else { |
| 220 | pcieHotplugMap += "0, " |
| 221 | } |
| 222 | } |
| 223 | |
| 224 | if b.IsPCIeHotplug(ctx, 7) { |
| 225 | pcieHotplugMap += "1 }" |
| 226 | } else { |
| 227 | pcieHotplugMap += "0 }" |
| 228 | } |
| 229 | |
| 230 | cur := DevTreeNode{ |
| 231 | Chip: "southbridge/intel/bd82x6x", |
| 232 | Comment: "Intel Series 6 Cougar Point PCH", |
| 233 | |
| 234 | Registers: map[string]string{ |
| 235 | "sata_interface_speed_support": "0x3", |
| 236 | "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), |
| 237 | "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), |
| 238 | "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), |
| 239 | "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), |
| 240 | "pcie_port_coalesce": "1", |
| 241 | "pcie_hotplug_map": pcieHotplugMap, |
| 242 | |
| 243 | "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), |
| 244 | |
| 245 | "p_cnt_throttling_supported": (FormatBool(FADT[104] == 1 && FADT[105] == 3)), |
| 246 | "c2_latency": FormatHexLE16(FADT[96:98]), |
| 247 | "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), |
| 248 | }, |
| 249 | PCISlots: []PCISlot{ |
| 250 | PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, |
| 251 | PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, |
| 252 | PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, |
| 253 | PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, |
| 254 | PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, |
| 255 | PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, |
| 256 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, |
| 257 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, |
| 258 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, |
| 259 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, |
| 260 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, |
| 261 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, |
| 262 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, |
| 263 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, |
| 264 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, |
| 265 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, |
| 266 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, |
| 267 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, |
| 268 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, |
| 269 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, |
| 270 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, |
| 271 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, |
| 272 | PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, |
| 273 | }, |
| 274 | } |
| 275 | |
| 276 | b.node = &cur |
| 277 | |
| 278 | xhciDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}] |
| 279 | |
| 280 | if ok { |
| 281 | cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8]) |
| 282 | cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0]) |
| 283 | cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4]) |
| 284 | } |
| 285 | |
| 286 | PutPCIChip(addr, cur) |
| 287 | PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") |
| 288 | |
| 289 | DSDTIncludes = append(DSDTIncludes, DSDTInclude{ |
| 290 | File: "southbridge/intel/bd82x6x/acpi/platform.asl", |
| 291 | }) |
| 292 | DSDTIncludes = append(DSDTIncludes, DSDTInclude{ |
| 293 | File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", |
| 294 | Comment: "global NVS and variables", |
| 295 | }) |
| 296 | DSDTIncludes = append(DSDTIncludes, DSDTInclude{ |
| 297 | File: "southbridge/intel/bd82x6x/acpi/sleepstates.asl", |
| 298 | }) |
| 299 | DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ |
| 300 | File: "southbridge/intel/bd82x6x/acpi/pch.asl", |
Stefan Reinauer | f2ccc43 | 2015-06-20 21:40:42 +0200 | [diff] [blame] | 301 | }, DSDTInclude{ |
| 302 | File: "southbridge/intel/bd82x6x/acpi/default_irq_route.asl", |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 303 | }) |
| 304 | |
| 305 | sb := Create(ctx, "early_southbridge.c") |
| 306 | defer sb.Close() |
| 307 | AddROMStageFile("early_southbridge.c", "") |
| 308 | sb.WriteString(`#include <stdint.h> |
| 309 | #include <string.h> |
| 310 | #include <lib.h> |
| 311 | #include <timestamp.h> |
| 312 | #include <arch/byteorder.h> |
| 313 | #include <arch/io.h> |
| 314 | #include <device/pci_def.h> |
| 315 | #include <device/pnp_def.h> |
| 316 | #include <cpu/x86/lapic.h> |
| 317 | #include <arch/acpi.h> |
| 318 | #include <console/console.h> |
| 319 | #include "northbridge/intel/sandybridge/sandybridge.h" |
| 320 | #include "northbridge/intel/sandybridge/raminit_native.h" |
| 321 | #include "southbridge/intel/bd82x6x/pch.h" |
Stefan Reinauer | eb960f1 | 2016-02-17 16:34:02 -0800 | [diff] [blame] | 322 | #include <southbridge/intel/common/gpio.h> |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 323 | #include <arch/cpu.h> |
| 324 | #include <cpu/x86/msr.h> |
| 325 | |
| 326 | void pch_enable_lpc(void) |
| 327 | { |
| 328 | `) |
| 329 | RestorePCI16Simple(sb, addr, 0x82) |
| 330 | RestorePCI32Simple(sb, addr, 0x84) |
| 331 | RestorePCI32Simple(sb, addr, 0x88) |
| 332 | RestorePCI32Simple(sb, addr, 0x8c) |
| 333 | RestorePCI32Simple(sb, addr, 0x90) |
| 334 | |
| 335 | RestorePCI16Simple(sb, addr, 0x80) |
| 336 | |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 337 | sb.WriteString(`} |
| 338 | |
| 339 | void rcba_config(void) |
| 340 | { |
| 341 | /* Disable devices. */ |
| 342 | `) |
| 343 | RestoreRCBA32(sb, inteltool, 0x3414) |
| 344 | RestoreRCBA32(sb, inteltool, 0x3418) |
| 345 | |
| 346 | sb.WriteString("\n}\n") |
| 347 | |
| 348 | sb.WriteString("const struct southbridge_usb_port mainboard_usb_ports[] = {\n") |
| 349 | |
| 350 | currentMap := map[uint32]int{ |
| 351 | 0x20000153: 0, |
| 352 | 0x20000f57: 1, |
| 353 | 0x2000055b: 2, |
| 354 | 0x20000f51: 3, |
| 355 | 0x2000094a: 4, |
| 356 | } |
| 357 | |
| 358 | for port := uint(0); port < 14; port++ { |
| 359 | var pinmask uint32 |
| 360 | OCPin := -1 |
| 361 | if port < 8 { |
| 362 | pinmask = inteltool.RCBA[0x35a0] |
| 363 | } else { |
| 364 | pinmask = inteltool.RCBA[0x35a4] |
| 365 | } |
| 366 | for pin := uint(0); pin < 4; pin++ { |
| 367 | if ((pinmask >> ((port % 8) + 8*pin)) & 1) != 0 { |
| 368 | OCPin = int(pin) |
| 369 | if port >= 8 { |
| 370 | OCPin += 4 |
| 371 | } |
| 372 | } |
| 373 | } |
| 374 | fmt.Fprintf(sb, "\t{ %d, %d, %d },\n", |
| 375 | ((inteltool.RCBA[0x359c]>>port)&1)^1, |
| 376 | currentMap[inteltool.RCBA[uint16(0x3500+4*port)]], |
| 377 | OCPin) |
| 378 | } |
| 379 | sb.WriteString("};\n") |
| 380 | |
| 381 | guessedMap := GuessSPDMap(ctx) |
| 382 | |
| 383 | sb.WriteString(` |
Vladimir Serbinenko | 609bd94 | 2016-01-31 14:00:54 +0100 | [diff] [blame] | 384 | void mainboard_early_init(int s3resume) |
| 385 | { |
| 386 | } |
| 387 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 388 | void mainboard_config_superio(void) |
| 389 | { |
| 390 | } |
| 391 | |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 392 | /* FIXME: Put proper SPD map here. */ |
Kyösti Mälkki | 4015608 | 2016-12-04 11:17:07 +0200 | [diff] [blame] | 393 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 394 | { |
| 395 | `) |
| 396 | for i, spd := range guessedMap { |
Kyösti Mälkki | 4015608 | 2016-12-04 11:17:07 +0200 | [diff] [blame] | 397 | fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x, id_only);\n", i, spd) |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 398 | } |
| 399 | sb.WriteString("}\n") |
| 400 | |
| 401 | gnvs := Create(ctx, "gnvs.c") |
| 402 | defer gnvs.Close() |
| 403 | |
| 404 | gnvs.WriteString(`#include <southbridge/intel/bd82x6x/nvs.h> |
| 405 | |
| 406 | /* FIXME: check this function. */ |
| 407 | void acpi_create_gnvs(global_nvs_t *gnvs) |
| 408 | { |
| 409 | /* Disable USB ports in S3 by default */ |
| 410 | gnvs->s3u0 = 0; |
| 411 | gnvs->s3u1 = 0; |
| 412 | |
| 413 | /* Disable USB ports in S5 by default */ |
| 414 | gnvs->s5u0 = 0; |
| 415 | gnvs->s5u1 = 0; |
| 416 | |
| 417 | // the lid is open by default. |
| 418 | gnvs->lids = 1; |
| 419 | |
| 420 | gnvs->tcrt = 100; |
| 421 | gnvs->tpsv = 90; |
| 422 | } |
| 423 | `) |
| 424 | |
| 425 | AddRAMStageFile("gnvs.c", "") |
| 426 | } |
| 427 | |
| 428 | func init() { |
| 429 | /* BD82X6X LPC */ |
Vladimir Serbinenko | 42d55e0 | 2016-01-02 01:47:26 +0100 | [diff] [blame] | 430 | for id := 0x1c40; id <= 0x1c5f; id++ { |
Vladimir Serbinenko | 6b2d83c | 2016-01-11 18:43:25 +0100 | [diff] [blame] | 431 | RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "BD82X6X"}) |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | /* C216 LPC */ |
Vladimir Serbinenko | 42d55e0 | 2016-01-02 01:47:26 +0100 | [diff] [blame] | 435 | for id := 0x1e41; id <= 0x1e5f; id++ { |
Vladimir Serbinenko | 6b2d83c | 2016-01-11 18:43:25 +0100 | [diff] [blame] | 436 | RegisterPCI(0x8086, uint16(id), bd82x6x{variant: "C216"}) |
Vladimir Serbinenko | 3129f79 | 2014-10-15 21:51:47 +0200 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | /* PCIe bridge */ |
| 440 | for _, id := range []uint16{ |
| 441 | 0x1c10, 0x1c12, 0x1c14, 0x1c16, |
| 442 | 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e, |
| 443 | 0x1e10, 0x1e12, 0x1e14, 0x1e16, |
| 444 | 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e, |
| 445 | } { |
| 446 | RegisterPCI(0x8086, id, GenericPCI{}) |
| 447 | } |
| 448 | |
| 449 | /* SMBus controller */ |
| 450 | RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"}) |
| 451 | RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) |
| 452 | |
| 453 | /* SATA */ |
| 454 | for _, id := range []uint16{ |
| 455 | 0x1c00, 0x1c01, 0x1c02, 0x1c03, |
| 456 | 0x1e00, 0x1e01, 0x1e02, 0x1e03, |
| 457 | } { |
| 458 | RegisterPCI(0x8086, id, GenericPCI{}) |
| 459 | } |
| 460 | |
| 461 | /* EHCI */ |
| 462 | for _, id := range []uint16{ |
| 463 | 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, |
| 464 | } { |
| 465 | RegisterPCI(0x8086, id, GenericPCI{}) |
| 466 | } |
| 467 | |
| 468 | /* XHCI */ |
| 469 | RegisterPCI(0x8086, 0x1e31, GenericPCI{}) |
| 470 | |
| 471 | /* ME and children */ |
| 472 | for _, id := range []uint16{ |
| 473 | 0x1c3a, 0x1c3b, 0x1c3c, 0x1c3d, |
| 474 | 0x1e3a, 0x1e3b, 0x1e3c, 0x1e3d, |
| 475 | } { |
| 476 | RegisterPCI(0x8086, id, GenericPCI{}) |
| 477 | } |
| 478 | |
| 479 | /* Ethernet */ |
| 480 | RegisterPCI(0x8086, 0x1502, GenericPCI{}) |
| 481 | |
| 482 | } |