Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <arch/acpi.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <stdint.h> |
| 25 | #include <delay.h> |
| 26 | #include <cpu/intel/model_206ax/model_206ax.h> |
| 27 | #include <device/device.h> |
| 28 | #include <device/pci.h> |
| 29 | #include <device/pci_ids.h> |
| 30 | #include <device/hypertransport.h> |
| 31 | #include <stdlib.h> |
| 32 | #include <string.h> |
| 33 | #include <bitops.h> |
| 34 | #include <cpu/cpu.h> |
| 35 | #include <boot/tables.h> |
| 36 | #include "chip.h" |
| 37 | #include "sandybridge.h" |
| 38 | |
| 39 | static int bridge_revision_id = -1; |
| 40 | |
| 41 | int bridge_silicon_revision(void) |
| 42 | { |
| 43 | if (bridge_revision_id < 0) { |
| 44 | uint8_t stepping = cpuid_eax(1) & 0xf; |
| 45 | uint8_t bridge_id = pci_read_config16( |
| 46 | dev_find_slot(0, PCI_DEVFN(0, 0)), |
| 47 | PCI_DEVICE_ID) & 0xf0; |
| 48 | bridge_revision_id = bridge_id | stepping; |
| 49 | } |
| 50 | return bridge_revision_id; |
| 51 | } |
| 52 | |
| 53 | /* Reserve everything between A segment and 1MB: |
| 54 | * |
| 55 | * 0xa0000 - 0xbffff: legacy VGA |
| 56 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 57 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 58 | */ |
| 59 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 60 | static const int legacy_hole_size_k = 384; |
| 61 | |
| 62 | int add_northbridge_resources(struct lb_memory *mem) |
| 63 | { |
| 64 | lb_add_memory_range(mem, LB_MEM_RESERVED, |
| 65 | legacy_hole_base_k * 1024, legacy_hole_size_k * 1024); |
| 66 | |
| 67 | #if CONFIG_CHROMEOS_RAMOOPS |
| 68 | lb_add_memory_range(mem, LB_MEM_RESERVED, |
| 69 | CONFIG_CHROMEOS_RAMOOPS_RAM_START, |
| 70 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE); |
| 71 | #endif |
| 72 | |
| 73 | /* Required for SandyBridge sighting 3715511 */ |
| 74 | lb_add_memory_range(mem, LB_MEM_RESERVED, 0x20000000, 0x00200000); |
| 75 | lb_add_memory_range(mem, LB_MEM_RESERVED, 0x40000000, 0x00200000); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
| 80 | static int get_pcie_bar(u32 *base, u32 *len) |
| 81 | { |
| 82 | device_t dev; |
| 83 | u32 pciexbar_reg; |
| 84 | |
| 85 | *base = 0; |
| 86 | *len = 0; |
| 87 | |
| 88 | dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
| 89 | if (!dev) |
| 90 | return 0; |
| 91 | |
| 92 | pciexbar_reg = pci_read_config32(dev, PCIEXBAR); |
| 93 | |
| 94 | if (!(pciexbar_reg & (1 << 0))) |
| 95 | return 0; |
| 96 | |
| 97 | switch ((pciexbar_reg >> 1) & 3) { |
| 98 | case 0: // 256MB |
| 99 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); |
| 100 | *len = 256 * 1024 * 1024; |
| 101 | return 1; |
| 102 | case 1: // 128M |
| 103 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); |
| 104 | *len = 128 * 1024 * 1024; |
| 105 | return 1; |
| 106 | case 2: // 64M |
| 107 | *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); |
| 108 | *len = 64 * 1024 * 1024; |
| 109 | return 1; |
| 110 | } |
| 111 | |
| 112 | return 0; |
| 113 | } |
| 114 | |
| 115 | /* IDG memory */ |
| 116 | uint64_t uma_memory_base=0, uma_memory_size=0; |
| 117 | |
| 118 | static void add_fixed_resources(struct device *dev, int index) |
| 119 | { |
| 120 | struct resource *resource; |
| 121 | u32 pcie_config_base, pcie_config_size; |
| 122 | |
| 123 | printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx " |
| 124 | "size=0x%llx\n", uma_memory_base, uma_memory_size); |
| 125 | resource = new_resource(dev, index); |
| 126 | resource->base = (resource_t) uma_memory_base; |
| 127 | resource->size = (resource_t) uma_memory_size; |
| 128 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 129 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 130 | |
| 131 | /* Clear these values here so they don't get used by MTRR code */ |
| 132 | uma_memory_base = 0; |
| 133 | uma_memory_size = 0; |
| 134 | |
| 135 | if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { |
| 136 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
| 137 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
| 138 | resource = new_resource(dev, index+1); |
| 139 | resource->base = (resource_t) pcie_config_base; |
| 140 | resource->size = (resource_t) pcie_config_size; |
| 141 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 142 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 143 | } |
| 144 | } |
| 145 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 146 | #if CONFIG_WRITE_HIGH_TABLES |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 147 | #include <cbmem.h> |
| 148 | #endif |
| 149 | |
| 150 | static void pci_domain_set_resources(device_t dev) |
| 151 | { |
| 152 | uint64_t tom, me_base, touud; |
| 153 | uint32_t tseg_base, uma_size, tolud; |
| 154 | uint16_t ggc; |
| 155 | unsigned long long tomk; |
| 156 | |
| 157 | /* Total Memory 2GB example: |
| 158 | * |
| 159 | * 00000000 0000MB-1992MB 1992MB RAM (writeback) |
| 160 | * 7c800000 1992MB-2000MB 8MB TSEG (SMRR) |
| 161 | * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached) |
| 162 | * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached) |
| 163 | * 7f200000 2034MB TOLUD |
| 164 | * 7f800000 2040MB MEBASE |
| 165 | * 7f800000 2040MB-2048MB 8MB ME UMA (uncached) |
| 166 | * 80000000 2048MB TOM |
| 167 | * 100000000 4096MB-4102MB 6MB RAM (writeback) |
| 168 | * |
| 169 | * Total Memory 4GB example: |
| 170 | * |
| 171 | * 00000000 0000MB-2768MB 2768MB RAM (writeback) |
| 172 | * ad000000 2768MB-2776MB 8MB TSEG (SMRR) |
| 173 | * ad800000 2776MB-2778MB 2MB GFX GTT (uncached) |
| 174 | * ada00000 2778MB-2810MB 32MB GFX UMA (uncached) |
| 175 | * afa00000 2810MB TOLUD |
| 176 | * ff800000 4088MB MEBASE |
| 177 | * ff800000 4088MB-4096MB 8MB ME UMA (uncached) |
| 178 | * 100000000 4096MB TOM |
| 179 | * 100000000 4096MB-5374MB 1278MB RAM (writeback) |
| 180 | * 14fe00000 5368MB TOUUD |
| 181 | */ |
| 182 | |
| 183 | /* Top of Upper Usable DRAM, including remap */ |
| 184 | touud = pci_read_config32(dev, TOUUD+4); |
| 185 | touud <<= 32; |
| 186 | touud |= pci_read_config32(dev, TOUUD); |
| 187 | |
| 188 | /* Top of Lower Usable DRAM */ |
| 189 | tolud = pci_read_config32(dev, TOLUD); |
| 190 | |
| 191 | /* Top of Memory - does not account for any UMA */ |
| 192 | tom = pci_read_config32(dev, 0xa4); |
| 193 | tom <<= 32; |
| 194 | tom |= pci_read_config32(dev, 0xa0); |
| 195 | |
| 196 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 197 | touud, tolud, tom); |
| 198 | |
| 199 | /* ME UMA needs excluding if total memory <4GB */ |
| 200 | me_base = pci_read_config32(dev, 0x74); |
| 201 | me_base <<= 32; |
| 202 | me_base |= pci_read_config32(dev, 0x70); |
| 203 | |
| 204 | printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base); |
| 205 | |
| 206 | tomk = tolud >> 10; |
| 207 | if (me_base == tolud) { |
| 208 | /* ME is from MEBASE-TOM */ |
| 209 | uma_size = (tom - me_base) >> 10; |
| 210 | /* Increment TOLUD to account for ME as RAM */ |
| 211 | tolud += uma_size << 10; |
| 212 | /* UMA starts at old TOLUD */ |
| 213 | uma_memory_base = tomk * 1024ULL; |
| 214 | uma_memory_size = uma_size * 1024ULL; |
| 215 | printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", |
| 216 | me_base, uma_size >> 10); |
| 217 | } |
| 218 | |
| 219 | /* Graphics memory comes next */ |
| 220 | ggc = pci_read_config16(dev, GGC); |
| 221 | if (!(ggc & 2)) { |
| 222 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 223 | |
| 224 | /* Graphics memory */ |
| 225 | uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL; |
| 226 | printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10); |
| 227 | tomk -= uma_size; |
| 228 | uma_memory_base = tomk * 1024ULL; |
| 229 | uma_memory_size += uma_size * 1024ULL; |
| 230 | |
| 231 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 232 | uma_size = ((ggc >> 8) & 0x3) * 1024ULL; |
| 233 | tomk -= uma_size; |
| 234 | uma_memory_base = tomk * 1024ULL; |
| 235 | uma_memory_size += uma_size * 1024ULL; |
| 236 | printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10); |
| 237 | } |
| 238 | |
| 239 | /* Calculate TSEG size from its base which must be below GTT */ |
| 240 | tseg_base = pci_read_config32(dev, 0xb8); |
| 241 | uma_size = (uma_memory_base - tseg_base) >> 10; |
| 242 | tomk -= uma_size; |
| 243 | uma_memory_base = tomk * 1024ULL; |
| 244 | uma_memory_size += uma_size * 1024ULL; |
| 245 | printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n", |
| 246 | tseg_base, uma_size >> 10); |
| 247 | |
| 248 | printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10); |
| 249 | |
| 250 | /* Report the memory regions */ |
| 251 | ram_resource(dev, 3, 0, legacy_hole_base_k); |
| 252 | ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, |
| 253 | (tomk - (legacy_hole_base_k + legacy_hole_size_k))); |
| 254 | |
| 255 | /* |
| 256 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 257 | * is remapped above TOM, TOUUD will account for both |
| 258 | */ |
| 259 | touud >>= 10; /* Convert to KB */ |
| 260 | if (touud > 4096 * 1024) { |
| 261 | ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); |
| 262 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
| 263 | (touud >> 10) - 4096); |
| 264 | } |
| 265 | |
| 266 | add_fixed_resources(dev, 6); |
| 267 | |
| 268 | assign_resources(dev->link_list); |
| 269 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 270 | #if CONFIG_WRITE_HIGH_TABLES |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 271 | /* Leave some space for ACPI, PIRQ and MP tables */ |
| 272 | high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; |
| 273 | high_tables_size = HIGH_MEMORY_SIZE; |
| 274 | #endif |
| 275 | } |
| 276 | |
| 277 | /* TODO We could determine how many PCIe busses we need in |
| 278 | * the bar. For now that number is hardcoded to a max of 64. |
| 279 | * See e7525/northbridge.c for an example. |
| 280 | */ |
| 281 | static struct device_operations pci_domain_ops = { |
| 282 | .read_resources = pci_domain_read_resources, |
| 283 | .set_resources = pci_domain_set_resources, |
| 284 | .enable_resources = NULL, |
| 285 | .init = NULL, |
| 286 | .scan_bus = pci_domain_scan_bus, |
| 287 | #if CONFIG_MMCONF_SUPPORT_DEFAULT |
| 288 | .ops_pci_bus = &pci_ops_mmconf, |
| 289 | #else |
| 290 | .ops_pci_bus = &pci_cf8_conf1, |
| 291 | #endif |
| 292 | }; |
| 293 | |
| 294 | static void mc_read_resources(device_t dev) |
| 295 | { |
| 296 | struct resource *resource; |
| 297 | |
| 298 | pci_dev_read_resources(dev); |
| 299 | |
| 300 | /* So, this is one of the big mysteries in the coreboot resource |
| 301 | * allocator. This resource should make sure that the address space |
| 302 | * of the PCIe memory mapped config space bar. But it does not. |
| 303 | */ |
| 304 | |
| 305 | /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ |
| 306 | resource = new_resource(dev, 0xcf); |
| 307 | resource->base = DEFAULT_PCIEXBAR; |
| 308 | resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ |
| 309 | resource->flags = |
| 310 | IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 311 | IORESOURCE_ASSIGNED; |
| 312 | printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", |
| 313 | (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); |
| 314 | } |
| 315 | |
| 316 | static void mc_set_resources(device_t dev) |
| 317 | { |
| 318 | struct resource *resource; |
| 319 | |
| 320 | /* Report the PCIe BAR */ |
| 321 | resource = find_resource(dev, 0xcf); |
| 322 | if (resource) { |
| 323 | report_resource_stored(dev, resource, "<mmconfig>"); |
| 324 | } |
| 325 | |
| 326 | /* And call the normal set_resources */ |
| 327 | pci_dev_set_resources(dev); |
| 328 | } |
| 329 | |
| 330 | static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 331 | { |
| 332 | if (!vendor || !device) { |
| 333 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 334 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 335 | } else { |
| 336 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 337 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 338 | } |
| 339 | } |
| 340 | |
| 341 | static void northbridge_dmi_init(struct device *dev) |
| 342 | { |
| 343 | u32 reg32; |
| 344 | |
| 345 | /* Clear error status bits */ |
| 346 | DMIBAR32(0x1c4) = 0xffffffff; |
| 347 | DMIBAR32(0x1d0) = 0xffffffff; |
| 348 | |
| 349 | /* Steps prior to DMI ASPM */ |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 350 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 351 | reg32 = DMIBAR32(0x250); |
| 352 | reg32 &= ~((1 << 22)|(1 << 20)); |
| 353 | reg32 |= (1 << 21); |
| 354 | DMIBAR32(0x250) = reg32; |
| 355 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 356 | |
| 357 | reg32 = DMIBAR32(0x238); |
| 358 | reg32 |= (1 << 29); |
| 359 | DMIBAR32(0x238) = reg32; |
| 360 | |
| 361 | if (bridge_silicon_revision() >= SNB_STEP_D0) { |
| 362 | reg32 = DMIBAR32(0x1f8); |
| 363 | reg32 |= (1 << 16); |
| 364 | DMIBAR32(0x1f8) = reg32; |
| 365 | } else if (bridge_silicon_revision() >= SNB_STEP_D1) { |
| 366 | reg32 = DMIBAR32(0x1f8); |
| 367 | reg32 &= ~(1 << 26); |
| 368 | reg32 |= (1 << 16); |
| 369 | DMIBAR32(0x1f8) = reg32; |
| 370 | |
| 371 | reg32 = DMIBAR32(0x1fc); |
| 372 | reg32 |= (1 << 12) | (1 << 23); |
| 373 | DMIBAR32(0x1fc) = reg32; |
| 374 | } |
| 375 | |
| 376 | /* Enable ASPM on SNB link, should happen before PCH link */ |
Vincent Palatin | 0ff99b7 | 2012-03-28 16:10:29 -0700 | [diff] [blame] | 377 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 378 | reg32 = DMIBAR32(0xd04); |
| 379 | reg32 |= (1 << 4); |
| 380 | DMIBAR32(0xd04) = reg32; |
| 381 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 382 | |
| 383 | reg32 = DMIBAR32(0x88); |
| 384 | reg32 |= (1 << 1) | (1 << 0); |
| 385 | DMIBAR32(0x88) = reg32; |
| 386 | } |
| 387 | |
| 388 | static void northbridge_init(struct device *dev) |
| 389 | { |
| 390 | u8 bios_reset_cpl; |
| 391 | |
| 392 | northbridge_dmi_init(dev); |
| 393 | |
| 394 | /* |
| 395 | * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU |
| 396 | * that BIOS has initialized memory and power management |
| 397 | */ |
| 398 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
| 399 | bios_reset_cpl |= 1; |
| 400 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 401 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 402 | |
| 403 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 404 | mdelay(1); |
| 405 | set_power_limits(28); |
| 406 | |
| 407 | /* Set here before graphics PM init */ |
| 408 | MCHBAR32(0x5500) = 0x00100001; |
| 409 | } |
| 410 | |
| 411 | static void northbridge_enable(device_t dev) |
| 412 | { |
| 413 | #if CONFIG_HAVE_ACPI_RESUME |
| 414 | switch (pci_read_config32(dev, SKPAD)) { |
| 415 | case 0xcafebabe: |
| 416 | printk(BIOS_DEBUG, "Normal boot.\n"); |
| 417 | acpi_slp_type=0; |
| 418 | break; |
| 419 | case 0xcafed00d: |
| 420 | printk(BIOS_DEBUG, "S3 Resume.\n"); |
| 421 | acpi_slp_type=3; |
| 422 | break; |
| 423 | default: |
| 424 | printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); |
| 425 | acpi_slp_type=0; |
| 426 | break; |
| 427 | } |
| 428 | #endif |
| 429 | } |
| 430 | |
| 431 | static struct pci_operations intel_pci_ops = { |
| 432 | .set_subsystem = intel_set_subsystem, |
| 433 | }; |
| 434 | |
| 435 | static struct device_operations mc_ops = { |
| 436 | .read_resources = mc_read_resources, |
| 437 | .set_resources = mc_set_resources, |
| 438 | .enable_resources = pci_dev_enable_resources, |
| 439 | .init = northbridge_init, |
| 440 | .enable = northbridge_enable, |
| 441 | .scan_bus = 0, |
| 442 | .ops_pci = &intel_pci_ops, |
| 443 | }; |
| 444 | |
| 445 | static const struct pci_driver mc_driver __pci_driver = { |
| 446 | .ops = &mc_ops, |
| 447 | .vendor = PCI_VENDOR_ID_INTEL, |
| 448 | .device = 0x0104, /* Sandy bridge */ |
| 449 | }; |
| 450 | |
| 451 | static const struct pci_driver mc_driver_1 __pci_driver = { |
| 452 | .ops = &mc_ops, |
| 453 | .vendor = PCI_VENDOR_ID_INTEL, |
| 454 | .device = 0x0154, /* Ivy bridge */ |
| 455 | }; |
| 456 | |
| 457 | static void cpu_bus_init(device_t dev) |
| 458 | { |
| 459 | initialize_cpus(dev->link_list); |
| 460 | } |
| 461 | |
| 462 | static void cpu_bus_noop(device_t dev) |
| 463 | { |
| 464 | } |
| 465 | |
| 466 | static struct device_operations cpu_bus_ops = { |
| 467 | .read_resources = cpu_bus_noop, |
| 468 | .set_resources = cpu_bus_noop, |
| 469 | .enable_resources = cpu_bus_noop, |
| 470 | .init = cpu_bus_init, |
| 471 | .scan_bus = 0, |
| 472 | }; |
| 473 | |
| 474 | static void enable_dev(device_t dev) |
| 475 | { |
| 476 | /* Set the operations if it is a special bus type */ |
| 477 | if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { |
| 478 | dev->ops = &pci_domain_ops; |
| 479 | } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { |
| 480 | dev->ops = &cpu_bus_ops; |
| 481 | } |
| 482 | } |
| 483 | |
| 484 | struct chip_operations northbridge_intel_sandybridge_ops = { |
| 485 | CHIP_NAME("Intel i7 (Sandybridge) integrated Northbridge") |
| 486 | .enable_dev = enable_dev, |
| 487 | }; |