Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2018 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <assert.h> |
Lijian Zhao | 68890b9 | 2019-03-27 17:06:41 -0700 | [diff] [blame] | 17 | #include <cpu/x86/msr.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <fsp/util.h> |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 20 | #include <intelblocks/pmclib.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 21 | #include <soc/iomap.h> |
Lijian Zhao | 68890b9 | 2019-03-27 17:06:41 -0700 | [diff] [blame] | 22 | #include <soc/msr.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 23 | #include <soc/pci_devs.h> |
| 24 | #include <soc/romstage.h> |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 25 | #include <vendorcode/google/chromeos/chromeos.h> |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 26 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 27 | #include "../chip.h" |
| 28 | |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 29 | static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) |
| 30 | { |
| 31 | unsigned int i; |
| 32 | uint32_t mask = 0; |
Lijian Zhao | fe701ee | 2018-10-25 09:29:10 -0700 | [diff] [blame] | 33 | const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH); |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 34 | |
| 35 | /* Set IGD stolen size to 64MB. */ |
| 36 | m_cfg->IgdDvmt50PreAlloc = 2; |
| 37 | m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; |
| 38 | m_cfg->IedSize = CONFIG_IED_REGION_SIZE; |
| 39 | m_cfg->SaGv = config->SaGv; |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 40 | if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 41 | m_cfg->UserBd = BOARD_TYPE_DESKTOP; |
| 42 | else |
| 43 | m_cfg->UserBd = BOARD_TYPE_ULT_ULX; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 44 | m_cfg->RMT = config->RMT; |
| 45 | |
| 46 | for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { |
| 47 | if (config->PcieRpEnable[i]) |
| 48 | mask |= (1 << i); |
| 49 | } |
| 50 | m_cfg->PcieRpEnableMask = mask; |
| 51 | m_cfg->PrmrrSize = config->PrmrrSize; |
| 52 | m_cfg->EnableC6Dram = config->enable_c6dram; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 53 | m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; |
Maulik V Vaghela | bfe4a59 | 2019-03-13 18:16:01 +0530 | [diff] [blame] | 54 | /* |
| 55 | * PcdDebugInterfaceFlags |
| 56 | * This config will allow coreboot to pass information to the FSP |
| 57 | * regarding which debug interface is being used. |
| 58 | * Debug Interfaces: |
| 59 | * BIT0-RAM, BIT1-Legacy Uart BIT3-USB3, BIT4-LPSS Uart, BIT5-TraceHub |
| 60 | * BIT2 - Not used. |
| 61 | */ |
| 62 | m_cfg->PcdDebugInterfaceFlags = |
| 63 | CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; |
| 64 | |
Ronak Kanabar | 250dfc0 | 2019-03-29 13:25:09 +0530 | [diff] [blame] | 65 | /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ |
| 66 | m_cfg->VmxEnable = CONFIG(ENABLE_VMX); |
Subrata Banik | cf32fd1 | 2018-12-19 18:02:17 +0530 | [diff] [blame] | 67 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 68 | #if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) |
Lijian Zhao | 7f1a0e6 | 2019-04-22 21:17:58 +0000 | [diff] [blame] | 69 | m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 70 | #endif |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 71 | |
Lijian Zhao | 68890b9 | 2019-03-27 17:06:41 -0700 | [diff] [blame] | 72 | /* Set CpuRatio to match existing MSR value */ |
| 73 | msr_t flex_ratio; |
| 74 | flex_ratio = rdmsr(MSR_FLEX_RATIO); |
| 75 | m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; |
Duncan Laurie | 52b5b58 | 2019-01-23 14:55:47 -0800 | [diff] [blame] | 76 | |
Lijian Zhao | fe701ee | 2018-10-25 09:29:10 -0700 | [diff] [blame] | 77 | /* If ISH is enabled, enable ISH elements */ |
| 78 | if (!dev) |
| 79 | m_cfg->PchIshEnable = 0; |
| 80 | else |
| 81 | m_cfg->PchIshEnable = dev->enabled; |
Lijian Zhao | 3ef7449 | 2018-12-06 17:29:55 -0800 | [diff] [blame] | 82 | |
| 83 | /* If HDA is enabled, enable HDA elements */ |
| 84 | dev = dev_find_slot(0, PCH_DEVFN_HDA); |
| 85 | if (!dev) |
| 86 | m_cfg->PchHdaEnable = 0; |
| 87 | else |
| 88 | m_cfg->PchHdaEnable = dev->enabled; |
| 89 | |
V Sowmya | 0bc3e3d | 2019-01-07 13:11:29 +0530 | [diff] [blame] | 90 | /* Enable IPU only if the device is enabled */ |
| 91 | m_cfg->SaIpuEnable = 0; |
| 92 | dev = pcidev_path_on_root(SA_DEVFN_IPU); |
| 93 | if (dev) |
| 94 | m_cfg->SaIpuEnable = dev->enabled; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
| 98 | { |
| 99 | const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); |
Duncan Laurie | 25b387a | 2018-11-08 15:48:14 -0700 | [diff] [blame] | 100 | const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS); |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 101 | assert(dev != NULL); |
| 102 | const config_t *config = dev->chip_info; |
| 103 | FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; |
| 104 | |
| 105 | soc_memory_init_params(m_cfg, config); |
| 106 | |
| 107 | /* Enable SMBus controller based on config */ |
Duncan Laurie | 25b387a | 2018-11-08 15:48:14 -0700 | [diff] [blame] | 108 | if (!smbus) |
| 109 | m_cfg->SmbusEnable = 0; |
| 110 | else |
| 111 | m_cfg->SmbusEnable = smbus->enabled; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 112 | |
Kane Chen | 3717256 | 2019-04-11 21:55:20 +0800 | [diff] [blame] | 113 | /* Set debug probe type */ |
| 114 | m_cfg->PlatformDebugConsent = |
| 115 | CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT; |
Rizwan Qureshi | 742c6fe | 2018-09-18 22:43:41 +0530 | [diff] [blame] | 116 | mainboard_memory_init_params(mupd); |
| 117 | } |
| 118 | |
| 119 | __weak void mainboard_memory_init_params(FSPM_UPD *mupd) |
| 120 | { |
| 121 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 122 | } |