Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: BSD-3-Clause |
| 2 | |
| 3 | ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) |
| 4 | |
Kangheui Won | b997b0a0 | 2021-04-29 15:19:03 +1000 | [diff] [blame] | 5 | subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage |
| 6 | |
Felix Held | e7a0202 | 2020-12-10 02:05:47 +0100 | [diff] [blame] | 7 | # Beware that all-y also adds the compilation unit to verstage on PSP |
Felix Held | 62ef88f | 2020-12-08 23:18:19 +0100 | [diff] [blame] | 8 | all-y += aoac.c |
Felix Held | 46cd1b5 | 2023-04-01 01:21:27 +0200 | [diff] [blame] | 9 | all-y += config.c |
| 10 | all-y += i2c.c |
Felix Held | c827278 | 2020-12-05 01:39:28 +0100 | [diff] [blame] | 11 | |
Felix Held | f008e0a | 2023-04-01 01:31:24 +0200 | [diff] [blame] | 12 | # all_x86-y adds the compilation unit to all stages that run on the x86 cores |
| 13 | all_x86-y += gpio.c |
| 14 | all_x86-y += uart.c |
| 15 | |
Felix Held | 153f92a | 2020-12-08 17:27:30 +0100 | [diff] [blame] | 16 | bootblock-y += early_fch.c |
Felix Held | 62afdb6 | 2022-01-10 23:37:58 +0100 | [diff] [blame] | 17 | bootblock-y += espi_util.c |
Felix Held | 44f4153 | 2020-12-09 02:01:16 +0100 | [diff] [blame] | 18 | |
Felix Held | 2421de6 | 2021-03-26 01:13:53 +0100 | [diff] [blame] | 19 | romstage-y += fsp_m_params.c |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 20 | |
Felix Held | 8602495 | 2021-02-03 23:44:28 +0100 | [diff] [blame] | 21 | ramstage-y += acpi.c |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 22 | ramstage-y += chip.c |
Felix Held | 060b8ad | 2021-02-05 22:51:33 +0100 | [diff] [blame] | 23 | ramstage-y += cpu.c |
Felix Held | 230dbd6 | 2021-01-28 23:40:52 +0100 | [diff] [blame] | 24 | ramstage-y += fch.c |
Felix Held | 793f371 | 2021-03-26 00:13:51 +0100 | [diff] [blame] | 25 | ramstage-y += fsp_s_params.c |
Felix Held | d5b51be | 2021-07-16 20:51:08 +0200 | [diff] [blame] | 26 | ramstage-y += graphics.c |
Felix Held | a24472a | 2021-07-13 18:21:27 +0200 | [diff] [blame] | 27 | ramstage-y += mca.c |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 28 | ramstage-y += root_complex.c |
Felix Held | e77d939 | 2021-03-11 19:37:32 +0100 | [diff] [blame] | 29 | ramstage-y += xhci.c |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 30 | |
Mathew King | 45a33b0 | 2021-03-04 15:32:50 -0700 | [diff] [blame] | 31 | smm-y += gpio.c |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 32 | smm-y += smihandler.c |
Raul E Rangel | f41ca1e | 2021-02-12 16:57:49 -0700 | [diff] [blame] | 33 | smm-$(CONFIG_DEBUG_SMI) += uart.c |
Felix Held | ee2a365 | 2021-02-09 23:43:17 +0100 | [diff] [blame] | 34 | |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 35 | CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include |
Felix Held | 8602495 | 2021-02-03 23:44:28 +0100 | [diff] [blame] | 36 | CPPFLAGS_common += -I$(src)/soc/amd/cezanne/acpi |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 37 | CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne |
Konrad Adamczyk | 86dfcb8 | 2023-06-28 12:23:08 +0000 | [diff] [blame] | 38 | CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/common |
Felix Held | 8d0a609 | 2021-01-14 01:40:50 +0100 | [diff] [blame] | 39 | |
Robert Zieba | b26d005 | 2022-01-24 16:37:47 -0700 | [diff] [blame] | 40 | # 0x40 accounts for the cbfs_file struct + filename + metadata structs, aligned to 64 bytes |
| 41 | # Building the cbfs image will fail if the offset isn't large enough |
| 42 | AMD_FW_AB_POSITION := 0x40 |
| 43 | |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 44 | CEZANNE_FW_A_POSITION=$(call int-add, \ |
Matt DeVillier | 163dbdd | 2023-06-29 16:56:09 -0500 | [diff] [blame] | 45 | $(call get_fmap_value,FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 46 | |
| 47 | CEZANNE_FW_B_POSITION=$(call int-add, \ |
Matt DeVillier | 163dbdd | 2023-06-29 16:56:09 -0500 | [diff] [blame] | 48 | $(call get_fmap_value,FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 49 | # |
| 50 | # PSP Directory Table items |
| 51 | # |
| 52 | # Certain ordering requirements apply, however these are ensured by amdfwtool. |
| 53 | # For more information see "AMD Platform Security Processor BIOS Architecture |
| 54 | # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). |
| 55 | # |
| 56 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 57 | |
Rob Barnes | e09b681 | 2021-04-15 17:21:19 -0600 | [diff] [blame] | 58 | ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y) |
| 59 | PSP_SOFTFUSE_BITS += 7 |
| 60 | endif |
| 61 | |
Raul E Rangel | fa4d051 | 2022-02-01 11:12:33 -0700 | [diff] [blame] | 62 | ifeq ($(CONFIG_PSP_INIT_ESPI),y) |
Rob Barnes | e09b681 | 2021-04-15 17:21:19 -0600 | [diff] [blame] | 63 | PSP_SOFTFUSE_BITS += 15 |
| 64 | endif |
| 65 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 66 | ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) |
| 67 | # Enable secure debug unlock |
| 68 | PSP_SOFTFUSE_BITS += 0 |
| 69 | OPT_TOKEN_UNLOCK="--token-unlock" |
Felix Held | dc2d356 | 2020-12-02 14:38:53 +0100 | [diff] [blame] | 70 | endif |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 71 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 72 | ifeq ($(CONFIG_PSP_LOAD_MP2_FW),y) |
| 73 | OPT_PSP_LOAD_MP2_FW="--load-mp2-fw" |
| 74 | else |
| 75 | # Disable MP2 firmware loading |
| 76 | PSP_SOFTFUSE_BITS += 29 |
| 77 | endif |
| 78 | |
Rob Barnes | 3437a6f | 2021-12-10 14:28:21 -0700 | [diff] [blame] | 79 | ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) |
Rob Barnes | 4454c9a | 2021-12-17 10:37:43 -0700 | [diff] [blame] | 80 | PSP_SOFTFUSE_BITS += 58 |
Rob Barnes | 3437a6f | 2021-12-10 14:28:21 -0700 | [diff] [blame] | 81 | endif |
| 82 | |
Martin Roth | fdad5ad | 2021-04-16 11:36:01 -0600 | [diff] [blame] | 83 | # Use additional Soft Fuse bits specified in Kconfig |
Zheng Bao | 17022bb | 2021-05-13 22:38:05 +0800 | [diff] [blame] | 84 | PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) |
Martin Roth | fdad5ad | 2021-04-16 11:36:01 -0600 | [diff] [blame] | 85 | |
Raul E Rangel | 97b8b17 | 2021-02-24 16:59:32 -0700 | [diff] [blame] | 86 | # type = 0x3a |
| 87 | ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y) |
| 88 | PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE) |
| 89 | endif |
| 90 | |
Zheng Bao | c5b912f7 | 2022-02-11 11:53:32 +0800 | [diff] [blame] | 91 | # type = 0x55 |
Zheng Bao | c5b912f7 | 2022-02-11 11:53:32 +0800 | [diff] [blame] | 92 | SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE) |
Zheng Bao | c5b912f7 | 2022-02-11 11:53:32 +0800 | [diff] [blame] | 93 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 94 | # |
| 95 | # BIOS Directory Table items - proper ordering is managed by amdfwtool |
| 96 | # |
| 97 | |
| 98 | # type = 0x60 |
Matt Papageorge | a37ec52 | 2021-02-22 19:36:34 -0600 | [diff] [blame] | 99 | PSP_APCB_FILES=$(APCB_SOURCES) $(APCB_SOURCES_RECOVERY) |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 100 | |
| 101 | # type = 0x61 |
| 102 | PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS) |
| 103 | |
| 104 | # type = 0x62 |
| 105 | PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img |
| 106 | PSP_ELF_FILE=$(objcbfs)/bootblock.elf |
Felix Held | 3b89c95 | 2022-11-22 20:02:46 +0100 | [diff] [blame] | 107 | PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') |
| 108 | PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 109 | |
Fred Reitberger | 2a1fc73 | 2023-07-17 09:09:42 -0400 | [diff] [blame] | 110 | ifneq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE),y) |
Felix Held | 4324bc6 | 2021-02-19 22:28:56 +0100 | [diff] [blame] | 111 | # type = 0x63 - construct APOB NV base/size from flash map |
| 112 | # The flashmap section used for this is expected to be named RW_MRC_CACHE |
Matt DeVillier | 163dbdd | 2023-06-29 16:56:09 -0500 | [diff] [blame] | 113 | APOB_NV_SIZE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_SIZE) |
| 114 | APOB_NV_BASE=$(call get_fmap_value,FMAP_SECTION_RW_MRC_CACHE_START) |
Fred Reitberger | 2a1fc73 | 2023-07-17 09:09:42 -0400 | [diff] [blame] | 115 | endif # !CONFIG_SOC_AMD_COMMON_BLOCK_APOB_NV_DISABLE |
Felix Held | 4324bc6 | 2021-02-19 22:28:56 +0100 | [diff] [blame] | 116 | |
Kangheui Won | b997b0a0 | 2021-04-29 15:19:03 +1000 | [diff] [blame] | 117 | ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) |
| 118 | # type = 0x6B - PSP Shared memory location |
| 119 | ifneq ($(CONFIG_PSP_SHAREDMEM_SIZE),0x0) |
| 120 | PSP_SHAREDMEM_SIZE=$(CONFIG_PSP_SHAREDMEM_SIZE) |
| 121 | PSP_SHAREDMEM_BASE=$(shell awk '$$3 == "_psp_sharedmem_dram" {printf "0x" $$1}' $(objcbfs)/bootblock.map) |
| 122 | endif |
| 123 | |
| 124 | # type = 0x52 - PSP Bootloader Userspace Application (verstage) |
| 125 | PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) |
| 126 | PSP_VERSTAGE_SIG_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_SIGNING_TOKEN)) |
| 127 | endif # CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK |
| 128 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 129 | # Helper function to return a value with given bit set |
Martin Roth | fdad5ad | 2021-04-16 11:36:01 -0600 | [diff] [blame] | 130 | # Soft Fuse type = 0xb - See #55758 (NDA) for bit definitions. |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 131 | set-bit=$(call int-shift-left, 1 $(call _toint,$1)) |
| 132 | PSP_SOFTFUSE=$(shell A=$(call int-add, \ |
Matt DeVillier | 0daefa5 | 2023-10-30 20:58:41 -0500 | [diff] [blame] | 133 | $(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A) |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 134 | |
| 135 | # |
| 136 | # Build the arguments to amdfwtool (order is unimportant). Missing file names |
| 137 | # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. |
| 138 | # |
| 139 | |
| 140 | add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) |
| 141 | |
Kangheui Won | b997b0a0 | 2021-04-29 15:19:03 +1000 | [diff] [blame] | 142 | OPT_VERSTAGE_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_FILE), --verstage) |
| 143 | OPT_VERSTAGE_SIG_FILE=$(call add_opt_prefix, $(PSP_VERSTAGE_SIG_FILE), --verstage_sig) |
| 144 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 145 | OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \ |
| 146 | $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \ |
| 147 | $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68)) |
| 148 | |
| 149 | OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) |
| 150 | OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) |
| 151 | OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest) |
| 152 | OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size) |
| 153 | |
Kangheui Won | b997b0a0 | 2021-04-29 15:19:03 +1000 | [diff] [blame] | 154 | OPT_PSP_SHAREDMEM_BASE=$(call add_opt_prefix, $(PSP_SHAREDMEM_BASE), --sharedmem) |
| 155 | OPT_PSP_SHAREDMEM_SIZE=$(call add_opt_prefix, $(PSP_SHAREDMEM_SIZE), --sharedmem-size) |
Felix Held | 4324bc6 | 2021-02-19 22:28:56 +0100 | [diff] [blame] | 156 | OPT_APOB_NV_SIZE=$(call add_opt_prefix, $(APOB_NV_SIZE), --apob-nv-size) |
| 157 | OPT_APOB_NV_BASE=$(call add_opt_prefix, $(APOB_NV_BASE),--apob-nv-base) |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 158 | OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) |
| 159 | OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) |
| 160 | OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag) |
| 161 | |
| 162 | OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse) |
| 163 | |
Raul E Rangel | 97b8b17 | 2021-02-24 16:59:32 -0700 | [diff] [blame] | 164 | OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) |
Zheng Bao | c5b912f7 | 2022-02-11 11:53:32 +0800 | [diff] [blame] | 165 | OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) |
Raul E Rangel | 97b8b17 | 2021-02-24 16:59:32 -0700 | [diff] [blame] | 166 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 167 | AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ |
| 168 | $(OPT_APOB_ADDR) \ |
Martin Roth | 0acf59d | 2023-03-08 15:18:24 -0700 | [diff] [blame] | 169 | $(OPT_DEBUG_AMDFWTOOL) \ |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 170 | $(OPT_PSP_BIOSBIN_FILE) \ |
| 171 | $(OPT_PSP_BIOSBIN_DEST) \ |
| 172 | $(OPT_PSP_BIOSBIN_SIZE) \ |
| 173 | $(OPT_PSP_SOFTFUSE) \ |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 174 | $(OPT_PSP_LOAD_MP2_FW) \ |
Felix Held | 5f5b7dd | 2021-02-12 20:51:55 +0100 | [diff] [blame] | 175 | --use-pspsecureos \ |
Felix Held | bb3e9ef | 2021-02-12 18:26:08 +0100 | [diff] [blame] | 176 | --load-s0i3 \ |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 177 | $(OPT_TOKEN_UNLOCK) \ |
Raul E Rangel | 97b8b17 | 2021-02-24 16:59:32 -0700 | [diff] [blame] | 178 | $(OPT_WHITELIST_FILE) \ |
Zheng Bao | c5b912f7 | 2022-02-11 11:53:32 +0800 | [diff] [blame] | 179 | $(OPT_SPL_TABLE_FILE) \ |
Kangheui Won | b997b0a0 | 2021-04-29 15:19:03 +1000 | [diff] [blame] | 180 | $(OPT_PSP_SHAREDMEM_BASE) \ |
| 181 | $(OPT_PSP_SHAREDMEM_SIZE) \ |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 182 | $(OPT_EFS_SPI_READ_MODE) \ |
| 183 | $(OPT_EFS_SPI_SPEED) \ |
| 184 | $(OPT_EFS_SPI_MICRON_FLAG) \ |
| 185 | --config $(CONFIG_AMDFW_CONFIG_FILE) \ |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 186 | --flashsize $(CONFIG_ROM_SIZE) |
| 187 | |
| 188 | $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ |
Kangheui Won | b997b0a0 | 2021-04-29 15:19:03 +1000 | [diff] [blame] | 189 | $(PSP_VERSTAGE_FILE) \ |
| 190 | $(PSP_VERSTAGE_SIG_FILE) \ |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 191 | $$(PSP_APCB_FILES) \ |
| 192 | $(DEP_FILES) \ |
| 193 | $(AMDFWTOOL) \ |
Kangheui Won | b997b0a0 | 2021-04-29 15:19:03 +1000 | [diff] [blame] | 194 | $(obj)/fmap_config.h \ |
| 195 | $(objcbfs)/bootblock.elf # this target also creates the .map file |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 196 | $(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set)) |
| 197 | rm -f $@ |
| 198 | @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" |
| 199 | $(AMDFWTOOL) \ |
| 200 | $(AMDFW_COMMON_ARGS) \ |
Felix Held | 4324bc6 | 2021-02-19 22:28:56 +0100 | [diff] [blame] | 201 | $(OPT_APOB_NV_SIZE) \ |
| 202 | $(OPT_APOB_NV_BASE) \ |
Kangheui Won | b997b0a0 | 2021-04-29 15:19:03 +1000 | [diff] [blame] | 203 | $(OPT_VERSTAGE_FILE) \ |
| 204 | $(OPT_VERSTAGE_SIG_FILE) \ |
Zheng Bao | 6bc0698 | 2023-02-14 13:26:31 +0800 | [diff] [blame] | 205 | --location $(CONFIG_AMD_FWM_POSITION) \ |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 206 | --multilevel \ |
| 207 | --output $@ |
| 208 | |
| 209 | $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) |
| 210 | rm -f $@ |
| 211 | @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" |
| 212 | $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ |
| 213 | --maxsize $(PSP_BIOSBIN_SIZE) |
| 214 | |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 215 | $(obj)/amdfw_a.rom: $(obj)/amdfw.rom |
| 216 | rm -f $@ |
| 217 | @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" |
| 218 | $(AMDFWTOOL) \ |
| 219 | $(AMDFW_COMMON_ARGS) \ |
| 220 | $(OPT_APOB_NV_SIZE) \ |
| 221 | $(OPT_APOB_NV_BASE) \ |
Fred Reitberger | e66ce2f | 2023-07-05 15:43:19 -0400 | [diff] [blame] | 222 | --location $(call _tohex,$(CEZANNE_FW_A_POSITION)) \ |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 223 | --anywhere \ |
| 224 | --multilevel \ |
| 225 | --output $@ |
| 226 | |
| 227 | $(obj)/amdfw_b.rom: $(obj)/amdfw.rom |
| 228 | rm -f $@ |
| 229 | @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" |
| 230 | $(AMDFWTOOL) \ |
| 231 | $(AMDFW_COMMON_ARGS) \ |
| 232 | $(OPT_APOB_NV_SIZE) \ |
| 233 | $(OPT_APOB_NV_BASE) \ |
Fred Reitberger | e66ce2f | 2023-07-05 15:43:19 -0400 | [diff] [blame] | 234 | --location $(call _tohex,$(CEZANNE_FW_B_POSITION)) \ |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 235 | --anywhere \ |
| 236 | --multilevel \ |
| 237 | --output $@ |
| 238 | |
| 239 | |
Matt DeVillier | f9fea86 | 2022-10-04 16:41:28 -0500 | [diff] [blame] | 240 | ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 241 | cbfs-files-y += apu/amdfw_a |
| 242 | apu/amdfw_a-file := $(obj)/amdfw_a.rom |
Robert Zieba | b26d005 | 2022-01-24 16:37:47 -0700 | [diff] [blame] | 243 | # Ensure this ends up at the beginning of the FW_MAIN_A fmap region |
| 244 | apu/amdfw_a-position := $(AMD_FW_AB_POSITION) |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 245 | apu/amdfw_a-type := raw |
Matt DeVillier | f9fea86 | 2022-10-04 16:41:28 -0500 | [diff] [blame] | 246 | endif |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 247 | |
Matt DeVillier | f9fea86 | 2022-10-04 16:41:28 -0500 | [diff] [blame] | 248 | ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 249 | cbfs-files-y += apu/amdfw_b |
| 250 | apu/amdfw_b-file := $(obj)/amdfw_b.rom |
Robert Zieba | b26d005 | 2022-01-24 16:37:47 -0700 | [diff] [blame] | 251 | # Ensure this ends up at the beginning of the FW_MAIN_B fmap region |
| 252 | apu/amdfw_b-position := $(AMD_FW_AB_POSITION) |
Kangheui Won | 1b2eeb1 | 2021-05-06 13:09:12 +1000 | [diff] [blame] | 253 | apu/amdfw_b-type := raw |
| 254 | endif |
| 255 | |
Zheng Bao | f51738d | 2021-01-20 16:43:52 +0800 | [diff] [blame] | 256 | endif # ($(CONFIG_SOC_AMD_CEZANNE),y) |