blob: 3a297f9e3871a05d20802617f8c76886f80cfb86 [file] [log] [blame]
Bill XIE11092462021-06-01 00:21:39 +08001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <bootblock_common.h>
4#include <device/pnp_ops.h>
5#include <northbridge/intel/sandybridge/raminit_native.h>
6#include <southbridge/intel/bd82x6x/pch.h>
7#include <superio/nuvoton/common/nuvoton.h>
8#include <superio/nuvoton/nct6779d/nct6779d.h>
9
10#define GLOBAL_DEV PNP_DEV(0x2e, 0)
11#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
12#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI)
13
14const struct southbridge_usb_port mainboard_usb_ports[] = {
15 { 1, 0, 0 },
16 { 1, 0, 0 },
17 { 1, 0, 1 },
18 { 1, 0, 1 },
19 { 1, 0, 2 },
20 { 1, 0, 2 },
21 { 1, 0, 3 },
22 { 1, 0, 3 },
23 { 1, 0, 4 },
24 { 1, 0, 4 },
25 { 1, 0, 6 },
26 { 1, 0, 5 },
27 { 1, 0, 5 },
28 { 1, 0, 6 },
29};
30
31void bootblock_mainboard_early_init(void)
32{
33 nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
34
35 /* Select SIO pin states */
36 pnp_write_config(GLOBAL_DEV, 0x1a, 0x02);
37 pnp_write_config(GLOBAL_DEV, 0x1b, 0x70);
38 pnp_write_config(GLOBAL_DEV, 0x1c, 0x10);
39 pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e);
40 pnp_write_config(GLOBAL_DEV, 0x22, 0xd7);
41 pnp_write_config(GLOBAL_DEV, 0x2a, 0x48);
42 pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
43
44 /* Power RAM in S3 */
45 pnp_set_logical_device(ACPI_DEV);
46 pnp_write_config(ACPI_DEV, 0xe4, 0x10);
47
48 nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
49
50 /* Enable UART */
51 nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
52}
53
54void mainboard_get_spd(spd_raw_data *spd, bool id_only)
55{
56 read_spd(&spd[0], 0x50, id_only);
57 read_spd(&spd[1], 0x51, id_only);
58 read_spd(&spd[2], 0x52, id_only);
59 read_spd(&spd[3], 0x53, id_only);
60}