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Angel Pons08da24e2020-04-03 01:21:24 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Damien Zammitd2b5b732017-10-04 20:07:47 +11002
Mike Banon33768dd2019-12-20 11:08:35 +03003#include <amdblocks/acpimmio.h>
4#include <bootblock_common.h>
Damien Zammitd2b5b732017-10-04 20:07:47 +11005#include <stdint.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +02006#include <device/pci_ops.h>
Damien Zammitb93fb1a2017-10-04 20:17:02 +11007#include <superio/ite/common/ite.h>
8#include <superio/ite/it8728f/it8728f.h>
9
Damien Zammitb93fb1a2017-10-04 20:17:02 +110010#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
11#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
12#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO)
13
14static void sbxxx_enable_48mhzout(void)
15{
Damien Zammitb93fb1a2017-10-04 20:17:02 +110016 u32 reg32;
Mike Banon33768dd2019-12-20 11:08:35 +030017
18 /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
Idwer Volleringc2ce3702020-01-05 01:44:25 +010019 reg32 = misc_read32(0x28);
Damien Zammitb93fb1a2017-10-04 20:17:02 +110020 reg32 &= 0xfff8ffff;
Idwer Volleringc2ce3702020-01-05 01:44:25 +010021 misc_write32(0x28, reg32);
Damien Zammitb93fb1a2017-10-04 20:17:02 +110022
Mike Banon33768dd2019-12-20 11:08:35 +030023 /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
Idwer Volleringc2ce3702020-01-05 01:44:25 +010024 reg32 = misc_read32(0x40);
Damien Zammitb93fb1a2017-10-04 20:17:02 +110025 reg32 &= 0xffffbffb;
Idwer Volleringc2ce3702020-01-05 01:44:25 +010026 misc_write32(0x40, reg32);
Damien Zammitb93fb1a2017-10-04 20:17:02 +110027}
Damien Zammitd2b5b732017-10-04 20:07:47 +110028
Mike Banon33768dd2019-12-20 11:08:35 +030029void bootblock_mainboard_early_init(void)
Damien Zammitd2b5b732017-10-04 20:07:47 +110030{
Damien Zammitb93fb1a2017-10-04 20:17:02 +110031 /* Enable the AcpiMmio space */
Michał Żygowskiaf258cc2019-12-01 17:42:04 +010032 pm_io_write8(0x24, 1);
Damien Zammitd2b5b732017-10-04 20:07:47 +110033
34 /* Set LPC decode enables. */
Elyes HAOUASa4faec32020-04-22 16:49:28 +020035 const pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
Damien Zammitd2b5b732017-10-04 20:07:47 +110036 pci_write_config32(dev, 0x44, 0xff03ffd5);
37
Elyes Haouas10a500e2022-04-30 08:45:44 +020038 /* enable SIO LPC decode at 0x2e/2f */
39 pci_or_config8(dev, 0x48, 3);
Damien Zammitb93fb1a2017-10-04 20:17:02 +110040
Elyes Haouas10a500e2022-04-30 08:45:44 +020041 /* enable serial decode at 0x3f8 */
42 pci_or_config8(dev, 0x44, 1 << 6);
Damien Zammitb93fb1a2017-10-04 20:17:02 +110043
Mike Banon33768dd2019-12-20 11:08:35 +030044 /* enable SIO clock */
Damien Zammitb93fb1a2017-10-04 20:17:02 +110045 sbxxx_enable_48mhzout();
Mike Banon33768dd2019-12-20 11:08:35 +030046
47 /* Enable serial output on it8728f */
Damien Zammitb93fb1a2017-10-04 20:17:02 +110048 ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
49 ite_kill_watchdog(GPIO_DEV);
50 ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Damien Zammitd2b5b732017-10-04 20:07:47 +110051}