Angel Pons | 08da24e | 2020-04-03 01:21:24 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Damien Zammit | d2b5b73 | 2017-10-04 20:07:47 +1100 | [diff] [blame] | 2 | |
Mike Banon | 33768dd | 2019-12-20 11:08:35 +0300 | [diff] [blame] | 3 | #include <amdblocks/acpimmio.h> |
| 4 | #include <bootblock_common.h> |
Damien Zammit | d2b5b73 | 2017-10-04 20:07:47 +1100 | [diff] [blame] | 5 | #include <stdint.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 7 | #include <superio/ite/common/ite.h> |
| 8 | #include <superio/ite/it8728f/it8728f.h> |
| 9 | |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 10 | #define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) |
| 11 | #define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) |
| 12 | #define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) |
| 13 | |
| 14 | static void sbxxx_enable_48mhzout(void) |
| 15 | { |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 16 | u32 reg32; |
Mike Banon | 33768dd | 2019-12-20 11:08:35 +0300 | [diff] [blame] | 17 | |
| 18 | /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ |
Idwer Vollering | c2ce370 | 2020-01-05 01:44:25 +0100 | [diff] [blame] | 19 | reg32 = misc_read32(0x28); |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 20 | reg32 &= 0xfff8ffff; |
Idwer Vollering | c2ce370 | 2020-01-05 01:44:25 +0100 | [diff] [blame] | 21 | misc_write32(0x28, reg32); |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 22 | |
Mike Banon | 33768dd | 2019-12-20 11:08:35 +0300 | [diff] [blame] | 23 | /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ |
Idwer Vollering | c2ce370 | 2020-01-05 01:44:25 +0100 | [diff] [blame] | 24 | reg32 = misc_read32(0x40); |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 25 | reg32 &= 0xffffbffb; |
Idwer Vollering | c2ce370 | 2020-01-05 01:44:25 +0100 | [diff] [blame] | 26 | misc_write32(0x40, reg32); |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 27 | } |
Damien Zammit | d2b5b73 | 2017-10-04 20:07:47 +1100 | [diff] [blame] | 28 | |
Mike Banon | 33768dd | 2019-12-20 11:08:35 +0300 | [diff] [blame] | 29 | void bootblock_mainboard_early_init(void) |
Damien Zammit | d2b5b73 | 2017-10-04 20:07:47 +1100 | [diff] [blame] | 30 | { |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 31 | /* Enable the AcpiMmio space */ |
Michał Żygowski | af258cc | 2019-12-01 17:42:04 +0100 | [diff] [blame] | 32 | pm_io_write8(0x24, 1); |
Damien Zammit | d2b5b73 | 2017-10-04 20:07:47 +1100 | [diff] [blame] | 33 | |
| 34 | /* Set LPC decode enables. */ |
Elyes HAOUAS | a4faec3 | 2020-04-22 16:49:28 +0200 | [diff] [blame] | 35 | const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); |
Damien Zammit | d2b5b73 | 2017-10-04 20:07:47 +1100 | [diff] [blame] | 36 | pci_write_config32(dev, 0x44, 0xff03ffd5); |
| 37 | |
Elyes Haouas | 10a500e | 2022-04-30 08:45:44 +0200 | [diff] [blame^] | 38 | /* enable SIO LPC decode at 0x2e/2f */ |
| 39 | pci_or_config8(dev, 0x48, 3); |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 40 | |
Elyes Haouas | 10a500e | 2022-04-30 08:45:44 +0200 | [diff] [blame^] | 41 | /* enable serial decode at 0x3f8 */ |
| 42 | pci_or_config8(dev, 0x44, 1 << 6); |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 43 | |
Mike Banon | 33768dd | 2019-12-20 11:08:35 +0300 | [diff] [blame] | 44 | /* enable SIO clock */ |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 45 | sbxxx_enable_48mhzout(); |
Mike Banon | 33768dd | 2019-12-20 11:08:35 +0300 | [diff] [blame] | 46 | |
| 47 | /* Enable serial output on it8728f */ |
Damien Zammit | b93fb1a | 2017-10-04 20:17:02 +1100 | [diff] [blame] | 48 | ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); |
| 49 | ite_kill_watchdog(GPIO_DEV); |
| 50 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Damien Zammit | d2b5b73 | 2017-10-04 20:07:47 +1100 | [diff] [blame] | 51 | } |