Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 3 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 5 | #include <console/console.h> |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ids.h> |
Elyes HAOUAS | bf0970e | 2019-03-21 11:10:03 +0100 | [diff] [blame] | 9 | #include <drivers/intel/gma/edid.h> |
| 10 | #include <drivers/intel/gma/opregion.h> |
| 11 | #include <drivers/intel/gma/libgfxinit.h> |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 12 | #include <string.h> |
| 13 | #include <device/pci_ops.h> |
Arthur Heymans | c51522f | 2016-08-27 01:09:19 +0200 | [diff] [blame] | 14 | #include <commonlib/helpers.h> |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 15 | #include <cbmem.h> |
| 16 | #include <southbridge/intel/i82801ix/nvs.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 17 | #include <types.h> |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 18 | |
| 19 | #include "drivers/intel/gma/i915_reg.h" |
| 20 | #include "chip.h" |
| 21 | #include "gm45.h" |
Vladimir Serbinenko | 8801011 | 2014-08-16 03:35:33 +0200 | [diff] [blame] | 22 | |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 23 | static struct resource *gtt_res = NULL; |
| 24 | |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 25 | u32 gtt_read(u32 reg) |
| 26 | { |
| 27 | return read32(res2mmio(gtt_res, reg, 0)); |
| 28 | } |
| 29 | |
Vladimir Serbinenko | 8801011 | 2014-08-16 03:35:33 +0200 | [diff] [blame] | 30 | void gtt_write(u32 reg, u32 data) |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 31 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 32 | write32(res2mmio(gtt_res, reg, 0), data); |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 33 | } |
| 34 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 35 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 36 | { |
| 37 | const global_nvs_t *gnvs_ptr = gnvs; |
| 38 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 39 | } |
| 40 | |
| 41 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 42 | { |
| 43 | global_nvs_t *gnvs_ptr = gnvs; |
| 44 | if (gnvs_ptr) |
| 45 | gnvs_ptr->aslb = aslb; |
| 46 | } |
| 47 | |
Nico Huber | d85a71a | 2016-11-27 14:43:12 +0100 | [diff] [blame] | 48 | static u32 get_cdclk(struct device *const dev) |
| 49 | { |
| 50 | const u16 cdclk_sel = |
| 51 | pci_read_config16 (dev, GCFGC_OFFSET) & GCFGC_CD_MASK; |
| 52 | switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { |
| 53 | case VCO_2666: |
| 54 | case VCO_4000: |
| 55 | case VCO_5333: |
| 56 | return cdclk_sel ? 333333333 : 222222222; |
| 57 | case VCO_3200: |
| 58 | return cdclk_sel ? 320000000 : 228571429; |
| 59 | default: |
| 60 | printk(BIOS_WARNING, |
| 61 | "Unknown VCO frequency, using default cdclk.\n"); |
| 62 | return 222222222; |
| 63 | } |
| 64 | } |
| 65 | |
Arthur Heymans | 12bed26 | 2016-11-24 13:23:05 +0100 | [diff] [blame] | 66 | static u32 freq_to_blc_pwm_ctl(struct device *const dev, |
| 67 | u16 pwm_freq, u8 duty_perc) |
| 68 | { |
| 69 | u32 blc_mod; |
| 70 | |
| 71 | blc_mod = get_cdclk(dev) / (128 * pwm_freq); |
| 72 | |
| 73 | if (duty_perc <= 100) |
| 74 | return (blc_mod << 16) | (blc_mod * duty_perc / 100); |
| 75 | else |
| 76 | return (blc_mod << 16) | blc_mod; |
| 77 | } |
| 78 | |
Arthur Heymans | 4d2d171 | 2018-11-29 12:25:31 +0100 | [diff] [blame] | 79 | u16 get_blc_pwm_freq_value(const char *edid_ascii_string) |
Arthur Heymans | c679b1f | 2018-11-29 12:21:12 +0100 | [diff] [blame] | 80 | { |
| 81 | static u16 blc_pwm_freq; |
| 82 | const struct blc_pwm_t *blc_pwm; |
| 83 | int i; |
| 84 | int blc_array_len; |
| 85 | |
| 86 | if (blc_pwm_freq > 0) |
| 87 | return blc_pwm_freq; |
| 88 | |
| 89 | blc_array_len = get_blc_values(&blc_pwm); |
| 90 | /* Find EDID string and pwm freq in lookup table */ |
| 91 | for (i = 0; i < blc_array_len; i++) { |
| 92 | if (!strcmp(blc_pwm[i].ascii_string, edid_ascii_string)) { |
| 93 | blc_pwm_freq = blc_pwm[i].pwm_freq; |
| 94 | printk(BIOS_DEBUG, "Found EDID string: %s in lookup table, pwm: %dHz\n", |
| 95 | blc_pwm[i].ascii_string, blc_pwm_freq); |
| 96 | break; |
| 97 | } |
| 98 | } |
| 99 | |
| 100 | if (i == blc_array_len) |
| 101 | printk(BIOS_NOTICE, "Your panels EDID `%s` wasn't found in the" |
| 102 | "lookup table.\n You may have issues with your panels" |
| 103 | "backlight.\n If you want to help improving coreboot" |
| 104 | "please report: this EDID string\n and the result" |
| 105 | "of `intel_read read BLC_PWM_CTL`" |
| 106 | "(from intel-gpu-tools)\n while running vendor BIOS\n", |
| 107 | edid_ascii_string); |
| 108 | |
| 109 | return blc_pwm_freq; |
| 110 | } |
| 111 | |
Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 112 | static void gma_pm_init_post_vbios(struct device *const dev, |
| 113 | const char *edid_ascii_string) |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 114 | { |
| 115 | const struct northbridge_intel_gm45_config *const conf = dev->chip_info; |
| 116 | |
| 117 | u32 reg32; |
Arthur Heymans | 12bed26 | 2016-11-24 13:23:05 +0100 | [diff] [blame] | 118 | u8 reg8; |
Arthur Heymans | c679b1f | 2018-11-29 12:21:12 +0100 | [diff] [blame] | 119 | u16 pwm_freq; |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 120 | |
| 121 | /* Setup Panel Power On Delays */ |
| 122 | reg32 = gtt_read(PP_ON_DELAYS); |
| 123 | if (!reg32) { |
| 124 | reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 125 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 126 | gtt_write(PP_ON_DELAYS, reg32); |
| 127 | } |
| 128 | |
| 129 | /* Setup Panel Power Off Delays */ |
| 130 | reg32 = gtt_read(PP_OFF_DELAYS); |
| 131 | if (!reg32) { |
| 132 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 133 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 134 | gtt_write(PP_OFF_DELAYS, reg32); |
| 135 | } |
| 136 | |
| 137 | /* Setup Panel Power Cycle Delay */ |
| 138 | if (conf->gpu_panel_power_cycle_delay) { |
Nico Huber | d85a71a | 2016-11-27 14:43:12 +0100 | [diff] [blame] | 139 | reg32 = (get_cdclk(dev) / 20000 - 1) |
| 140 | << PP_REFERENCE_DIVIDER_SHIFT; |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 141 | reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; |
| 142 | gtt_write(PP_DIVISOR, reg32); |
| 143 | } |
| 144 | |
| 145 | /* Enable Backlight */ |
| 146 | gtt_write(BLC_PWM_CTL2, (1 << 31)); |
Arthur Heymans | 12bed26 | 2016-11-24 13:23:05 +0100 | [diff] [blame] | 147 | reg8 = 100; |
| 148 | if (conf->duty_cycle != 0) |
| 149 | reg8 = conf->duty_cycle; |
Arthur Heymans | c679b1f | 2018-11-29 12:21:12 +0100 | [diff] [blame] | 150 | pwm_freq = get_blc_pwm_freq_value(edid_ascii_string); |
| 151 | if (pwm_freq == 0 && conf->default_pwm_freq != 0) |
Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 152 | pwm_freq = conf->default_pwm_freq; |
| 153 | |
Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 154 | if (pwm_freq == 0) |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 155 | gtt_write(BLC_PWM_CTL, 0x06100610); |
| 156 | else |
Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 157 | gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, pwm_freq, |
| 158 | reg8)); |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 159 | } |
| 160 | |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 161 | static void gma_func0_init(struct device *dev) |
| 162 | { |
| 163 | u32 reg32; |
Arthur Heymans | 53485d2 | 2017-04-30 08:29:54 +0200 | [diff] [blame] | 164 | u8 *mmio; |
| 165 | u8 edid_data_lvds[128]; |
| 166 | struct edid edid_lvds; |
Arthur Heymans | a6ce5d3 | 2019-01-06 01:33:07 +0100 | [diff] [blame] | 167 | const struct northbridge_intel_gm45_config *const conf = dev->chip_info; |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 168 | |
| 169 | /* IGD needs to be Bus Master */ |
| 170 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 171 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 172 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 173 | |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 174 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
Arthur Heymans | 53485d2 | 2017-04-30 08:29:54 +0200 | [diff] [blame] | 175 | if (gtt_res == NULL) |
| 176 | return; |
| 177 | mmio = res2mmio(gtt_res, 0, 0); |
Timothy Pearson | e7f7090 | 2015-04-06 22:01:23 -0500 | [diff] [blame] | 178 | |
Arthur Heymans | a6ce5d3 | 2019-01-06 01:33:07 +0100 | [diff] [blame] | 179 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 180 | if (!CONFIG(MAINBOARD_USE_LIBGFXINIT)) { |
Nico Huber | ee352cd | 2016-01-09 23:15:53 +0100 | [diff] [blame] | 181 | /* PCI Init, will run VBIOS */ |
Arthur Heymans | 53485d2 | 2017-04-30 08:29:54 +0200 | [diff] [blame] | 182 | printk(BIOS_DEBUG, "Initialising IGD using VBIOS\n"); |
Nico Huber | ee352cd | 2016-01-09 23:15:53 +0100 | [diff] [blame] | 183 | pci_dev_init(dev); |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 184 | } |
| 185 | |
Arthur Heymans | 53485d2 | 2017-04-30 08:29:54 +0200 | [diff] [blame] | 186 | printk(BIOS_DEBUG, "LVDS EDID\n"); |
Arthur Heymans | 8da2286 | 2017-08-06 15:56:30 +0200 | [diff] [blame] | 187 | intel_gmbus_read_edid(mmio + GMBUS0, GMBUS_PORT_PANEL, 0x50, |
| 188 | edid_data_lvds, sizeof(edid_data_lvds)); |
Arthur Heymans | 53485d2 | 2017-04-30 08:29:54 +0200 | [diff] [blame] | 189 | intel_gmbus_stop(mmio + GMBUS0); |
| 190 | decode_edid(edid_data_lvds, sizeof(edid_data_lvds), &edid_lvds); |
| 191 | |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 192 | /* Post VBIOS init */ |
Arthur Heymans | 20cb85f | 2017-04-29 14:31:32 +0200 | [diff] [blame] | 193 | gma_pm_init_post_vbios(dev, edid_lvds.ascii_string); |
Nico Huber | b851cc6 | 2016-01-09 23:27:16 +0100 | [diff] [blame] | 194 | |
Arthur Heymans | 29e5358 | 2019-10-12 17:39:31 +0200 | [diff] [blame] | 195 | if (CONFIG(MAINBOARD_USE_LIBGFXINIT) && !acpi_is_wakeup_s3()) { |
Arthur Heymans | a6ce5d3 | 2019-01-06 01:33:07 +0100 | [diff] [blame] | 196 | int vga_disable = (pci_read_config16(dev, D0F0_GGC) & 2) >> 1; |
| 197 | if (vga_disable) { |
| 198 | printk(BIOS_INFO, |
| 199 | "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); |
| 200 | } else { |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 201 | int lightup_ok; |
| 202 | gma_gfxinit(&lightup_ok); |
Arthur Heymans | a6ce5d3 | 2019-01-06 01:33:07 +0100 | [diff] [blame] | 203 | /* Linux relies on VBT for panel info. */ |
| 204 | generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CANTIGA"); |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 205 | } |
Nico Huber | f2dd049 | 2017-10-29 15:42:44 +0100 | [diff] [blame] | 206 | } |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 207 | |
| 208 | intel_gma_restore_opregion(); |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 209 | } |
| 210 | |
Matt DeVillier | e91883f | 2020-03-30 22:20:03 -0500 | [diff] [blame] | 211 | static void gma_generate_ssdt(struct device *device) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 212 | { |
Matt DeVillier | e91883f | 2020-03-30 22:20:03 -0500 | [diff] [blame] | 213 | const struct northbridge_intel_gm45_config *chip = device->chip_info; |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 214 | |
Matt DeVillier | e91883f | 2020-03-30 22:20:03 -0500 | [diff] [blame] | 215 | drivers_intel_gma_displays_ssdt_generate(&chip->gfx); |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 216 | } |
| 217 | |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 218 | static unsigned long |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame^] | 219 | gma_write_acpi_tables(const struct device *const dev, |
Patrick Rudolph | f6aa7d9 | 2017-09-29 18:28:23 +0200 | [diff] [blame] | 220 | unsigned long current, |
| 221 | struct acpi_rsdp *const rsdp) |
| 222 | { |
| 223 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
| 224 | global_nvs_t *gnvs; |
| 225 | |
| 226 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
| 227 | return current; |
| 228 | |
| 229 | current += sizeof(igd_opregion_t); |
| 230 | |
| 231 | /* GNVS has been already set up */ |
| 232 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 233 | if (gnvs) { |
| 234 | /* IGD OpRegion Base Address */ |
| 235 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
| 236 | } else { |
| 237 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
| 238 | } |
| 239 | |
| 240 | current = acpi_align_current(current); |
| 241 | return current; |
| 242 | } |
| 243 | |
| 244 | static const char *gma_acpi_name(const struct device *dev) |
| 245 | { |
| 246 | return "GFX0"; |
| 247 | } |
| 248 | |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 249 | static struct pci_operations gma_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 250 | .set_subsystem = pci_dev_set_subsystem, |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 251 | }; |
| 252 | |
| 253 | static struct device_operations gma_func0_ops = { |
Matt DeVillier | e91883f | 2020-03-30 22:20:03 -0500 | [diff] [blame] | 254 | .read_resources = pci_dev_read_resources, |
| 255 | .set_resources = pci_dev_set_resources, |
| 256 | .enable_resources = pci_dev_enable_resources, |
| 257 | .acpi_fill_ssdt = gma_generate_ssdt, |
| 258 | .init = gma_func0_init, |
Matt DeVillier | e91883f | 2020-03-30 22:20:03 -0500 | [diff] [blame] | 259 | .ops_pci = &gma_pci_ops, |
| 260 | .acpi_name = gma_acpi_name, |
| 261 | .write_acpi_tables = gma_write_acpi_tables, |
Vladimir Serbinenko | 6481e10 | 2014-08-10 23:48:11 +0200 | [diff] [blame] | 262 | }; |
| 263 | |
| 264 | static const unsigned short pci_device_ids[] = |
| 265 | { |
| 266 | 0x2a42, 0 |
| 267 | }; |
| 268 | |
| 269 | static const struct pci_driver gma __pci_driver = { |
| 270 | .ops = &gma_func0_ops, |
| 271 | .vendor = PCI_VENDOR_ID_INTEL, |
| 272 | .devices = pci_device_ids, |
| 273 | }; |